Semiconductor device

ABSTRACT

Provided is a semiconductor device in which deterioration of electrical characteristics can be suppressed. The semiconductor device includes a first oxide semiconductor layer over an insulating surface, a second oxide semiconductor layer over the first oxide semiconductor layer, a source electrode layer and a drain electrode layer whose one surfaces are in contact with part of the first oxide semiconductor layer and part of the second oxide semiconductor layer, a third oxide semiconductor layer over the first oxide semiconductor layer and the second oxide semiconductor layer, a gate insulating film over the third oxide semiconductor layer, and a gate electrode layer over the gate insulating film. The second oxide semiconductor layer wholly overlaps with the first oxide semiconductor layer. Part of the third oxide semiconductor layer is in contact with the other surfaces of the source electrode layer and the drain electrode layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an object, a method, or a manufacturing method. The present invention relates to a process, a machine, manufacture, or a composition of matter. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a storage device, an arithmetic unit, an imaging device, a method for driving any of them, or a method for manufacturing any of them.

In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are embodiments of semiconductor devices. In some cases, a storage device, a display device, or an electronic device includes a semiconductor device.

2. Description of the Related Art

Attention has been focused on a technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface (also referred to as a thin film transistor (TFT)). The transistor is used in a wide range of electronic devices such as an integrated circuit (IC) and an image display device (display device). A silicon-based semiconductor material is widely known as a material for a semiconductor thin film applicable to a transistor. As another example, an oxide semiconductor has been attracting attention.

For example, a transistor whose active layer includes an amorphous oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn) is disclosed in Patent Document 1.

REFERENCE Patent Document

[Patent Document 1] Japanese Published Patent Application No. 2006-165528

SUMMARY OF THE INVENTION

In general, high integration of a circuit requires miniaturization of a transistor. However, it is known that miniaturization of a transistor causes deterioration of electrical characteristics, such as on-state current, threshold voltage, and an S value (subthreshold value), of the transistor.

One object of one embodiment of the present invention is to provide a semiconductor device in which deterioration of electrical characteristics which becomes more noticeable as the semiconductor device is miniaturized can be suppressed. Another object is to provide a semiconductor device having a high degree of integration. Another object is to provide a semiconductor device in which deterioration of on-state current characteristics is reduced. Another object is to provide a semiconductor device with low power consumption. Another object is to provide a semiconductor device with high reliability. Another object is to provide a semiconductor device which can retain data even when power supply is stopped.

Note that the descriptions of these objects do not disturb the existence of other objects. Note that in one embodiment of the present invention, there is no need to achieve all the objects. Other objects are apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

One embodiment of the present invention relates to a semiconductor device including stacked oxide semiconductor layers.

One embodiment of the present invention is a semiconductor device including a first oxide semiconductor layer over an insulating surface, a second oxide semiconductor layer over the first oxide semiconductor layer, a source electrode layer and a drain electrode layer in contact with part of the first oxide semiconductor layer and part of the second oxide semiconductor layer, a third oxide semiconductor layer over the first oxide semiconductor layer and the second oxide semiconductor layer, a gate insulating film over the third oxide semiconductor layer, and a gate electrode layer over the gate insulating film. The second oxide semiconductor layer whose area is smaller than that of the first oxide semiconductor layer wholly overlaps with the first oxide semiconductor layer. The third oxide semiconductor layer is in contact with part of the source electrode layer and part of the drain electrode layer.

Note that in this specification and the like, ordinal numbers such as “first” and “second” are used in order to avoid confusion among components and do not limit the components numerically.

In the first oxide semiconductor layer, a region not overlapping with the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer may be in contact with the third oxide semiconductor layer.

In the first oxide semiconductor layer, a region not overlapping with the second oxide semiconductor layer may be thinner than a region overlapping with the second oxide semiconductor layer.

It is preferable that, in a cross section of the semiconductor device in a channel width direction, the length (W_(T)) of a top surface of the second oxide semiconductor layer and the length (W_(S)) of one of side surfaces of the second oxide semiconductor layer satisfy a relation 0.3 W_(S)≦W_(T)≦3W_(S) (W_(T) is greater than or equal to 0.3 W_(S) and less than or equal to 3W_(S)).

Further, a conduction band minimum of the first oxide semiconductor layer and a conduction band minimum of the third oxide semiconductor layer are preferably closer to a vacuum level than a conduction band minimum of the second oxide semiconductor layer by 0.05 eV or more and 2 eV or less.

Each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer preferably includes a crystal in which c-axes are aligned.

A crystal in a side surface portion of the second oxide semiconductor layer and a crystal in the third oxide semiconductor layer covering the side surface portion are preferably connected by indium and oxygen.

According to one embodiment of the present invention, any of the following semiconductor devices can be provided: a semiconductor device in which deterioration of electrical characteristics which becomes more noticeable as the semiconductor device is miniaturized can be suppressed, a semiconductor device having a high degree of integration, a semiconductor device in which deterioration of on-state current characteristics is reduced, a semiconductor device with low power consumption, a semiconductor device with high reliability, and a semiconductor device which can retain data even when power supply is stopped.

Note that the descriptions of these effects do not disturb the existence of other effects. In one embodiment of the present invention, there is no need to obtain all the effects. Other effects are apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1D are a top view and cross-sectional views illustrating a transistor.

FIGS. 2A and 2B each illustrate a band structure of oxide semiconductor layers.

FIG. 3 is an enlarged cross-sectional view of a transistor.

FIGS. 4A and 4B are each a cross-sectional view of a transistor in a channel width direction.

FIGS. 5A and 5B are each a cross-sectional view of a transistor in a channel width direction.

FIG. 6 is a cross-sectional view of a transistor in a channel width direction.

FIG. 7 is a cross-sectional view of a transistor in a channel width direction.

FIGS. 8A to 8C illustrate a method for manufacturing a transistor.

FIGS. 9A to 9C illustrate a method for manufacturing a transistor.

FIGS. 10A to 10D illustrate an embodiment of a crystal structure of an oxide semiconductor layer.

FIGS. 11A and 11B are a cross-sectional view and a circuit diagram of a semiconductor device.

FIG. 12 is a circuit diagram of a semiconductor device.

FIG. 13 is a block diagram of a semiconductor device.

FIG. 14 is a circuit diagram of a storage device.

FIGS. 15A to 15C illustrate electronic devices in which semiconductor devices can be used.

FIGS. 16A to 16D are a top view and cross-sectional views illustrating a transistor.

FIGS. 17A and 17B are each a cross-sectional view of a transistor in a channel width direction.

FIG. 18 is a cross-sectional view of a transistor in a channel width direction.

FIG. 19 is a cross-sectional view of a transistor in a channel width direction.

FIGS. 20A to 20C illustrate a method for manufacturing a transistor.

FIGS. 21A to 21C illustrate a method for manufacturing a transistor.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments are described in detail with reference to the drawings. Note that the present invention is not limited to the following description and it is readily appreciated by those skilled in the art that modes and details can be modified in various ways without departing from the spirit and the scope of the present invention. Therefore, the present invention should not be limited to the descriptions of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is omitted in some cases.

Note that in this specification and the like, when it is explicitly described that X and Y are connected, the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected are included therein. Here, each of X and Y denotes an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, or the like). Accordingly, without being limited to a predetermined connection relation, for example, a connection relation shown in the drawings and texts, another connection relation is included.

In the case where X and Y are electrically connected, one or more elements (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, and a load) that enable an electrical connection between X and Y can be connected between X and Y, for example. Note that the switch is controlled to be turned on or off. That is, the switch has a function of determining whether current flows or not by being turned on or off (becoming an on state and an off state). Alternatively, the switch has a function of selecting and changing a current path.

In the case where X and Y are functionally connected, one or more circuits (e.g., a logic circuit such as an inverter, a NAND circuit, or a NOR circuit; a signal converter circuit such as a DA converter circuit, an AD converter circuit, or a gamma correction circuit; a potential level converter circuit such as a power supply circuit (e.g., a step-up circuit or a step-down circuit) or a level shifter circuit for changing the potential level of a signal; a voltage source; a current source; a switching circuit; an amplifier circuit such as a circuit that can increase signal amplitude, the amount of current, or the like, an operational amplifier, a differential amplifier circuit, a source follower circuit, or a buffer circuit; a signal generation circuit; a memory circuit; and a control circuit) that enable a functional connection between X and Y can be connected between X and Y, for example. Note that for example, in the case where a signal output from X is transmitted to Y even when another circuit is interposed between X and Y, X and Y are functionally connected.

Note that when it is explicitly described that X and Y are connected, the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit provided therebetween), the case where X and Y are functionally connected (i.e., the case where X and Y are functionally connected with another circuit provided therebetween), and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit provided therebetween) are included therein. That is, when it is explicitly described that “X and Y are electrically connected”, the description is the same as the case where it is explicitly only described that “X and Y are connected”.

Even when independent components are electrically connected to each other in a circuit diagram, one component has functions of a plurality of components in some cases. For example, when part of a wiring also functions as an electrode, one conductive film functions as the wiring and the electrode. Thus, an “electrical connection” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.

Note that in this specification and the like, a transistor can be formed using any of a variety of substrates. The type of a substrate is not limited to a certain type. Examples of the substrate include a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate including stainless steel foil, a tungsten substrate, a substrate including tungsten foil, a flexible substrate, an attachment film, paper including a fibrous material, and a base material film. Examples of a glass substrate include a barium borosilicate glass substrate, an aluminoborosilicate glass substrate, and a soda lime glass substrate. For a flexible substrate, a flexible synthetic resin such as plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyether sulfone (PES), or acrylic can be used, for example. Examples of an attachment film include attachment films formed using polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, and the like. Examples of a base film include a base film formed using polyester, polyamide, polyimide, inorganic vapor deposition film, paper, and the like. Specifically, when a transistor is formed using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, a transistor with few variations in characteristics, size, shape, or the like, high current supply capability, and a small size can be formed. By forming a circuit using such a transistor, power consumption of the circuit can be reduced or the circuit can be highly integrated.

Note that a transistor may be formed using one substrate, and then, the transistor may be transferred to another substrate. Examples of a substrate to which a transistor is transferred include, in addition to the above-described substrates over which transistors can be formed, a paper substrate, a cellophane substrate, a stone substrate, a wood substrate, a cloth substrate (including a natural fiber (e.g., silk, cotton, or hemp), a synthetic fiber (e.g., nylon, polyurethane, or polyester), a regenerated fiber (e.g., acetate, cupra, rayon, or regenerated polyester), or the like), a leather substrate, a rubber substrate, and the like. With the use of such a substrate, a transistor with excellent properties, a transistor with low power consumption, or a device with high durability can be formed, high heat resistance can be provided, or a reduction in weight or thinning can be achieved.

(Embodiment 1)

In this embodiment, a semiconductor device of one embodiment of the present invention is described with reference to drawings.

FIGS. 1A to 1D are a top view and cross-sectional views which illustrate a transistor of one embodiment of the present invention. FIG. 1A is the top view. FIG. 1B illustrates a cross section taken along a dashed-dotted line A1-A2 in FIG. 1A. FIG. 1C illustrates a cross section taken along a dashed-dotted line A3-A4 in FIG. 1A. FIG. 1D illustrates a cross section taken along a dashed-dotted line A5-A6 in FIG. 1A. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG. 1A. In some cases, the direction of the dashed-dotted line A1-A2 is referred to as a channel length direction, and the direction of the dashed-dotted line A3-A4 is referred to as a channel width direction.

A transistor 100 illustrated in FIGS. 1A to 1D includes a base insulating film 120 formed over a substrate 110, a first oxide semiconductor layer 131 formed over the base insulating film 120, a second oxide semiconductor layer 132 formed over the first oxide semiconductor layer 131, a source electrode layer 140 and a drain electrode layer 150 in contact with part of the first oxide semiconductor layer 131 and part of the second oxide semiconductor layer 132, a third oxide semiconductor layer 133 formed over the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132, a gate insulating film 160 formed over the third oxide semiconductor layer 133, and a gate electrode layer 170 formed over the gate insulating film 160. The second oxide semiconductor layer 132 whose area is smaller than that of the first oxide semiconductor layer 131 wholly overlaps with the first oxide semiconductor layer 131. The third oxide semiconductor layer 133 is in contact with part of the source electrode layer 140 and part of the drain electrode layer 150.

As in a transistor 101 illustrated in FIGS. 16A to 16D, the first oxide semiconductor layer 131 may have a structure in which a region in contact with the source electrode layer 140 or the drain electrode layer 150 is thinner than a region overlapping with the second oxide semiconductor layer 132.

Further, an oxide insulating layer 180 may be formed over the gate insulating film 160 and the gate electrode layer 170. The oxide insulating layer 180 may be provided as needed and another insulating layer may be further provided thereover. The first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133 are collectively referred to as an oxide semiconductor layer 130.

Note that functions of a “source” and a “drain” of a transistor are sometimes replaced with each other when a transistor of opposite polarity is used or when the direction of current flowing is changed in circuit operation, for example. Thus, the terms “source” and “drain” can be used to denote the drain and the source, respectively, in this specification.

The substrate 110 is not limited to a simple supporting substrate, and may be a substrate where another device such as a transistor is formed. In that case, at least one of the gate electrode layer 170, the source electrode layer 140, and the drain electrode layer 150 of the transistor 100 may be electrically connected to the above device.

The base insulating film 120 can have a function of supplying oxygen to the oxide semiconductor layer 130 as well as a function of preventing diffusion of impurities from the substrate 110. For this reason, the base insulating film 120 is preferably an insulating film containing oxygen and more preferably, the base insulating film 120 is an insulating film containing oxygen in which the oxygen content is higher than that in the stoichiometric composition. In the case where the substrate 110 is provided with another device as described above, the base insulating film 120 also has a function as an interlayer insulating film. In that case, the base insulating film 120 is preferably subjected to planarization treatment such as chemical mechanical polishing (CMP) treatment so as to have a flat surface.

Further, in a region where a channel of the transistor 100 is formed, the oxide semiconductor layer 130 has a structure in which the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133 are stacked in this order from the substrate 110 side. Furthermore, in the first oxide semiconductor layer 131, a region not overlapping with the second oxide semiconductor layer 132, the source electrode layer 140, and the drain electrode layer 150 is in contact with the third oxide semiconductor layer 133, which means that the second oxide semiconductor layer 132 is surrounded by the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133.

Here, for the second oxide semiconductor layer 132, for example, an oxide semiconductor whose electron affinity (an energy difference between a vacuum level and the conduction band minimum) is higher than those of the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 is used. The electron affinity can be obtained by subtracting an energy difference between the conduction band minimum and the valence band maximum (what is called an energy gap) from an energy difference between the vacuum level and the valence band maximum (what is called an ionization potential).

The first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 each contain one or more kinds of metal elements forming the second oxide semiconductor layer 132. For example, the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are preferably formed using an oxide semiconductor whose conduction band minimum is closer to a vacuum level than that of the second oxide semiconductor layer 132. Further, the energy difference of the conduction band minimum between the second oxide semiconductor layer 132 and the first oxide semiconductor layer 131 and the energy difference of the conduction band minimum between the second oxide semiconductor layer 132 and the third oxide semiconductor layer 133 are each preferably greater than or equal to 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV and smaller than or equal to 2 eV, 1 eV, 0.5 eV, or 0.4 eV.

In such a structure, when an electric field is applied to the gate electrode layer 170, a channel is formed in the second oxide semiconductor layer 132 whose conduction band minimum is the lowest in the oxide semiconductor layer 130. In other words, the third oxide semiconductor layer 133 is formed between the second oxide semiconductor layer 132 and the gate insulating film 160, whereby a structure in which the channel of the transistor is not in contact with the gate insulating film 160 is obtained.

Further, since the first oxide semiconductor layer 131 contains one or more metal elements contained in the second oxide semiconductor layer 132, an interface state is less likely to be formed at the interface of the second oxide semiconductor layer 132 with the first oxide semiconductor layer 131 than at the interface with the base insulating film 120 on the assumption that the second oxide semiconductor layer 132 is in contact with the base insulating film 120. The interface state sometimes forms a channel, leading to a change in the threshold voltage of the transistor. Thus, with the first oxide semiconductor layer 131, variation in the electrical characteristics of the transistor, such as a threshold voltage, can be reduced. Further, the reliability of the transistor can be improved.

Furthermore, since the third oxide semiconductor layer 133 contains one or more metal elements contained in the second oxide semiconductor layer 132, scattering of carriers is less likely to occur at the interface of the second oxide semiconductor layer 132 with the third oxide semiconductor layer 133 than at the interface with the gate insulating film 160 on the assumption that the second oxide semiconductor layer 132 is in contact with the gate insulating film 160. Thus, with the third oxide semiconductor layer 133, the field-effect mobility of the transistor can be increased.

For the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133, for example, a material containing Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf with a higher atomic ratio than that used for the second oxide semiconductor layer 132 can be used. Specifically, an atomic ratio of any of the above metal elements in the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 is 1.5 times or more, preferably 2 times or more, further preferably 3 times or more as much as that in the second oxide semiconductor layer 132. Any of the above metal elements is strongly bonded to oxygen and thus has a function of suppressing generation of an oxygen vacancy in the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133. That is, an oxygen vacancy is less likely to be generated in the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 than in the second oxide semiconductor layer 132.

Note that when each of the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133 is an In-M-Zn oxide containing at least indium, zinc, and M (M is a metal such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf), and the first oxide semiconductor layer 131 has an atomic ratio of In to M and Zn which is x₁:y₁:z₁, the second oxide semiconductor layer 132 has an atomic ratio of In to M and Zn which is x₂:y₂:z₂, and the third oxide semiconductor layer 133 has an atomic ratio of In to M and Zn which is x₃:y₃:z₃, each of y₁/x₁ and y₃/x₃ is preferably larger than y₂/x₂. Each of y₁/x₁ and y₃/x₃ is 1.5 times or more, preferably 2 times or more, further preferably 3 times or more as large as y₂/x₂. At this time, when y₂ is greater than or equal to x₂ in the second oxide semiconductor layer 132, the transistor can have stable electrical characteristics. However, when y₂ is 3 times or more as large as x₂, the field-effect mobility of the transistor is reduced; accordingly, y₂ is preferably less than 3 times x₂.

Note that in this specification, an atomic ratio used for describing the composition of an oxide semiconductor layer can be also used as the atomic ratio of a base material. Table 1 shows examples of the compositions of targets formed using an In—Ga—Zn oxide material, which are measured by inductively coupled plasma mass spectrometry (ICP-MS) and the compositions of In—Ga—Zn oxide films formed using the targets by a sputtering method. Table 1 shows that Zn in an oxide film is less than that in its target in some cases.

TABLE 1 Composition (Atomic Ratio of In:Ga:Zn) IGZO Target 1:1:1 1:3:2 1:3:4 IGZO Film 1.0:1.0:0.7 1.0:2.9:1.2 1.0:3.0:2.6

In the case where an oxide semiconductor layer is deposited by a sputtering method using an oxide semiconductor material as a target, the composition of the oxide semiconductor layer might be different from that of the target, which is a base material, depending on the kind or a ratio of a sputtering gas, the density of the target, or deposition conditions. Thus, in this specification, an atomic ratio used for describing the composition of an oxide semiconductor layer is also used as the atomic ratio of a base material. For example, in the case where a sputtering method is used for deposition, an In—Ga—Zn oxide film whose atomic ratio of In to Ga and Zn is 1:1:1 can be also understood as an In—Ga—Zn oxide film formed using an In—Ga—Zn—O material whose atomic ratio of In to Ga and Zn is 1:1:1 as a target.

Further, in the case where Zn and O are not taken into consideration, the proportion of In and the proportion of M in each of the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are preferably less than 50 atomic % and greater than or equal to 50 atomic %, respectively, and further preferably less than 25 atomic % and greater than or equal to 75 atomic %, respectively. In addition, in the case where Zn and O are not taken into consideration, the proportion of In and the proportion of M in the second oxide semiconductor layer 132 are preferably greater than or equal to 25 atomic % and less than 75 atomic %, respectively, and further preferably greater than or equal to 34 atomic % and less than 66 atomic %, respectively.

The thicknesses of the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are each greater than or equal to 3 nm and less than or equal to 100 nm, preferably greater than or equal to 3 nm and less than or equal to 50 nm. The thickness of the second oxide semiconductor layer 132 is greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, further preferably greater than or equal to 3 nm and less than or equal to 50 nm.

For the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133, an oxide semiconductor containing indium, zinc, and gallium can be used, for example. Note that the second oxide semiconductor layer 132 preferably contains indium because carrier mobility can be increased.

Note that stable electrical characteristics can be effectively imparted to a transistor in which an oxide semiconductor layer serves as a channel by reducing the concentration of impurities in the oxide semiconductor layer to make the oxide semiconductor layer intrinsic or substantially intrinsic. The term “substantially intrinsic” refers to the state where an oxide semiconductor layer has a carrier density lower than 1×10¹⁷/cm³, preferably lower than 1×10¹⁵/cm³, further preferably lower than 1×10¹³/cm³.

Further, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal element other than main components are impurities. For example, hydrogen and nitrogen form donor levels to increase the carrier density, and silicon forms impurity levels in the oxide semiconductor layer. The impurity levels serve as traps and might cause electrical characteristics of the transistor to deteriorate. Thus, it is preferable to reduce the concentration of the impurities in the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133, and at interfaces between the layers.

In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, in SIMS (secondary ion mass spectrometry), for example, the concentration of silicon at a certain depth of the oxide semiconductor layer or in a region of the oxide semiconductor layer is preferably lower than 1×10¹⁹ atoms/cm³, more preferably lower than 5×10¹⁸ atoms/cm³, still more preferably lower than 1×10¹⁸ atoms/cm³. Further, the concentration of hydrogen at a certain depth of the oxide semiconductor layer or in a region of the oxide semiconductor layer is preferably lower than or equal to 2×10²⁰ atoms/cm³, more preferably lower than or equal to 5×10¹⁹ atoms/cm³, still more preferably lower than or equal to 1×10¹⁹ atoms/cm³, yet still more preferably lower than or equal to 5×10¹⁸ atoms/cm³. Further, the concentration of nitrogen at a certain depth of the oxide semiconductor layer or in a region of the oxide semiconductor layer is preferably lower than 5×10¹⁹ atoms/cm³, more preferably lower than or equal to 5×10¹⁸ atoms/cm³, still more preferably lower than or equal to 1×10¹⁸ atoms/cm³, yet still more preferably lower than or equal to 5×10¹⁷ atoms/cm³.

In the case where the oxide semiconductor layer includes crystals, high concentration of silicon or carbon might reduce the crystallinity of the oxide semiconductor layer. In order not to lower the crystallinity of the oxide semiconductor layer, for example, the concentration of silicon at a certain depth of the oxide semiconductor layer or in a region of the oxide semiconductor layer may be lower than 1×10¹⁹ atoms/cm³, preferably lower than 5×10¹⁸ atoms/cm³, more preferably lower than 1×10¹⁸ atoms/cm³. Further, the concentration of carbon at a certain depth of the oxide semiconductor layer or in a region of the oxide semiconductor layer may be lower than 1×10¹⁹ atoms/cm³, preferably lower than 5×10¹⁸ atoms/cm³, more preferably lower than 1×10¹⁸ atoms/cm³, for example.

A transistor in which the above-described highly purified oxide semiconductor layer is used for a channel formation region has an extremely low off-state current. In the case where the voltage between a source and a drain is set to about 0.1 V, 5 V, or 10 V, for example, the off-state current standardized on the channel width of the transistor can be as low as several yoctoamperes per micrometer to several zeptoamperes per micrometer.

Note that as the gate insulating film of the transistor, an insulating film containing silicon is used in many cases; thus, it is preferable that, as in the transistor of one embodiment of the present invention, a region of the oxide semiconductor layer, which serves as a channel, be not in contact with the gate insulating film for the above-described reason. In the case where a channel is formed at the interface between the gate insulating film and the oxide semiconductor layer, scattering of carriers occurs at the interface, whereby the field-effect mobility of the transistor is reduced in some cases. Also from the view of the above, it is preferable that the region of the oxide semiconductor layer, which serves as a channel, be separated from the gate insulating film.

Accordingly, with the oxide semiconductor layer 130 having a stacked-layer structure including the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133, a channel can be formed in the second oxide semiconductor layer 132; thus, the transistor can have a high field-effect mobility and stable electrical characteristics.

Next, the band structure of the oxide semiconductor layer 130 is described. A stack corresponding to the oxide semiconductor layer 130 in which an In—Ga—Zn oxide having an energy gap of 3.5 eV was used as a layer corresponding to each of the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 and an In—Ga—Zn oxide having an energy gap of 3.15 eV was used as a layer corresponding to the second oxide semiconductor layer 132 was fabricated, and the band structure thereof was analyzed.

The thickness of each of the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133 was 10 nm. The energy gap was measured with the use of a spectroscopic ellipsometer (UT-300 manufactured by HORIBA Jobin Yvon). Further, the energy difference between the vacuum level and the valence band maximum was measured using an ultraviolet photoelectron spectroscopy (UPS) device (VersaProbe, ULVAC-PHI, Inc.).

FIG. 2A is part of a schematic band structure showing an energy difference (electron affinity) between the vacuum level and the conduction band minimum of each layer, which is calculated by subtracting the energy gap from the energy difference between the vacuum level and the valence band maximum. FIG. 2A is a band diagram showing the case where silicon oxide films are provided in contact with the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133. Here, Ev represents energy of the vacuum level, EcI1 and EcI2 each represent the conduction band minimum of the silicon oxide film, EcS1 represents the conduction band minimum of the first oxide semiconductor layer 131, EcS2 represents the conduction band minimum of the second oxide semiconductor layer 132, and EcS3 represents the conduction band minimum of the third oxide semiconductor layer 133.

As shown in FIG. 2A, the conduction band minimums of the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133 successively vary. This can be understood also from the fact that the compositions of the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133 are close to one another and oxygen is easily diffused among the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133. Thus, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133 have a continuous physical property although they have different compositions and form a stack. In the drawings, interfaces between the oxide semiconductor layers of the stack are indicated by dotted lines.

The oxide semiconductor layer 130 in which layers containing the same main components are stacked is formed to have not only a simple stacked-layer structure of the layers but also a continuous energy band (here, in particular, a well structure having a U shape in which the conduction band minimums successively vary between layers). In other words, the stacked-layer structure is formed such that there exist no impurities which form a defect level such as a trap center or a recombination center at each interface. If impurities exist between the stacked oxide semiconductor layers, the continuity of the energy band is lost and carriers disappear by a trap or recombination.

Note that FIG. 2A shows the case where EcS1 and EcS3 are similar to each other; however, EcS1 and EcS3 may be different from each other. For example, part of the band structure in the case where EcS1 is higher than EcS3 is shown as in FIG. 2B.

For example, when EcS1 is equal to EcS3, an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:6:4, or 1:9:6 can be used for the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 and an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:1:1, 5:5:6, or 3:1:2 can be used for the second oxide semiconductor layer 132. Further, when EcS1 is higher than EcS3, an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:6:4 or 1:9:6 can be used for the first oxide semiconductor layer 131, an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:1:1, 5:5:6, or 3:1:2 can be used for the second oxide semiconductor layer 132, and an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:3:2, 1:3:3, 1:3:4, or 1:3:6 can be used for the third oxide semiconductor layer 133, for example.

According to FIGS. 2A and 2B, the second oxide semiconductor layer 132 of the oxide semiconductor layer 130 serves as a well, so that a channel is formed in the second oxide semiconductor layer 132 in a transistor including the oxide semiconductor layer 130. Note that since the conduction band minimum successively varies, the oxide semiconductor layer 130 can also be referred to as a U-shaped well. Further, a channel formed to have such a structure can also be referred to as a buried channel.

Note that trap levels due to impurities or defects might be formed in the vicinity of the interface between an insulating film such as a silicon oxide film and each of the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133. The second oxide semiconductor layer 132 can be distanced away from the trap levels owing to existence of the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133. However, when the energy difference between EcS1 and EcS2 or the energy difference between EcS3 and EcS2 is small, an electron in the second oxide semiconductor layer 132 might reach the trap level by passing over the energy difference. When the electron is trapped in the trap level, a negative fixed charge is caused at the interface with the insulating film, whereby the threshold voltage of the transistor is shifted in the positive direction.

Thus, to reduce a change in the threshold voltage of the transistor, energy differences between EcS2 and each of EcS1 and EcS3 are necessary. Each of the energy differences is preferably greater than or equal to 0.1 eV, further preferably greater than or equal to 0.15 eV.

Note that the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133 preferably contain crystal parts. In particular, when a crystal in which c-axes are aligned is used, the transistor can have stable electrical characteristics.

In the case where an In—Ga—Zn oxide is used for the oxide semiconductor layer 130, it is preferable that the third oxide semiconductor layer 133 contain less In than the second oxide semiconductor layer 132 so that diffusion of In to the gate insulating film is prevented.

For the source electrode layer 140 and the drain electrode layer 150, a conductive material which is easily bonded to oxygen is preferably used. For example, Al, Cr, Cu, Ta, Ti, Mo, or W can be used. Among the materials, in particular, it is preferable to use Ti which is easily bonded to oxygen or to use W with a high melting point, which allows subsequent process temperatures to be relatively high. Note that the conductive material which is easily bonded to oxygen includes, in its category, a material to which oxygen is easily diffused.

When the conductive material which is easily bonded to oxygen is in contact with an oxide semiconductor layer, a phenomenon occurs in which oxygen in the oxide semiconductor layer is diffused to the conductive material which is easily bonded to oxygen. The phenomenon noticeably occurs when the temperature is high. Since the fabrication process of the transistor involves some heat treatment steps, the above phenomenon causes generation of oxygen vacancies in the vicinity of a region which is in the oxide semiconductor layer and is in contact with the source electrode layer or the drain electrode layer. The oxygen vacancies bond to hydrogen slightly contained in the film, whereby the region is changed to an n-type region. Thus, the n-type region can serve as a source or a drain of the transistor.

The n-type region is illustrated in the enlarged cross-sectional view (a cross section in the channel width direction) of the transistor in FIG. 3. A boundary 135 indicated by a dotted line in the second oxide semiconductor layer 132 is a boundary between an intrinsic semiconductor region and an n-type semiconductor region. In the second oxide semiconductor layer 132, a region near the source electrode layer 140 or the drain electrode layer 150 becomes an n-type region. The boundary 135 is schematically illustrated here, but actually, the boundary is not clearly seen in some cases. Although FIG. 3 shows the boundary 135 extending in the lateral direction in the second oxide semiconductor layer 132, a region of the second oxide semiconductor layer 132 sandwiched between the first oxide semiconductor layer 131 and the source electrode layer 140 or the drain electrode layer 150 becomes n-type entirely in the thickness direction, in some cases. Further, although not illustrated, an n-type region may be formed in the first oxide semiconductor layer 131 or the third oxide semiconductor layer 133.

In the case of forming a transistor with an extremely short channel length, an n-type region which is formed by the generation of oxygen vacancies sometimes extends in the channel length direction of the transistor. In that case, electrical characteristics of the transistor change; for example, the threshold voltage is shifted, or on and off states of the transistor is hard to be controlled with the gate voltage (in which case the transistor is turned on). Accordingly, when a transistor with an extremely short channel length is formed, it is not always preferable that a conductive material which is easily bonded to oxygen be used for a source electrode layer and a drain electrode layer.

In such a case, a conductive material which is less likely to be bonded to oxygen than the above material is preferably used for the source electrode layer 140 and the drain electrode layer 150. As the conductive material which is not easily bonded to oxygen, for example, a material containing tantalum nitride, titanium nitride, or ruthenium or the like can be used. Note that in the case where the conductive material is in contact with the second oxide semiconductor layer 132, the source electrode layer 140 and the drain electrode layer 150 may each have a structure in which the conductive material which is not easily bonded to oxygen and the above-described conductive material that is easily bonded to oxygen are stacked.

The gate insulating film 160 can be formed using an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The gate insulating film 160 may be a stack including any of the above materials.

For the gate electrode layer 170, a conductive film formed using Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Ta, W, or the like can be used. The gate electrode layer may be a stack including any of the above materials. Alternatively, a conductive film containing nitrogen may be used for the gate electrode layer.

The oxide insulating layer 180 may be formed over the gate insulating film 160 and the gate electrode layer 170. The oxide insulating layer 180 can be formed using an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The oxide insulating layer 180 may be a stack including any of the above materials.

Here, the oxide insulating layer 180 preferably contains excess oxygen. An oxide insulating layer containing excess oxygen refers to an oxide insulating layer from which oxygen can be released by heat treatment or the like. The oxide insulating layer containing excess oxygen is preferably a film in which the amount of released oxygen when converted into oxygen atoms is 1.0×10¹⁹ atoms/cm³ or more in thermal desorption spectroscopy analysis. Oxygen released from the oxide insulating layer 180 can be diffused to the channel formation region in the oxide semiconductor layer 130 through the gate insulating film 160, so that oxygen vacancies formed in the channel formation region can be filled with the oxygen. In this manner, electrical characteristics of the transistor can be stable.

High integration of a semiconductor device requires miniaturization of a transistor. However, it is known that miniaturization of a transistor causes deterioration of electrical characteristics of the transistor. In particular, a reduction in on-state current, which is directly caused by a decrease in channel width, is significant.

FIGS. 4A and 4B are each a cross-sectional view in the channel width direction of a conventional transistor including an oxide semiconductor layer. Each transistor includes a base insulating film 220 over a substrate 210, an oxide semiconductor layer 230 formed over the base insulating film, a gate insulating film 260 formed over the oxide semiconductor layer, and a gate electrode 270.

In the transistor in FIG. 4A, the length (W_(T)) of the top surface of the oxide semiconductor layer in the channel width direction is sufficiently larger than the thickness of the oxide semiconductor layer 230. In such a case, the channel width can be defined as W_(T).

Since an electric field from the gate electrode 270 to a side surface of the oxide semiconductor layer 230 is not applied to the entire oxide semiconductor layer 230, a channel is not sufficiently formed in the side surface of the oxide semiconductor layer 230. Further, since a ratio of the length (W_(S1), W_(S2)) of the side surface corresponding to the thickness of the oxide semiconductor layer 230 to the length (W_(T)) of the top surface is small, even if a channel is formed, the contribution of the channel is estimated to be small. Thus, it can be said that as W_(T) becomes short, in other words, as the transistor is miniaturized, the on-state current is reduced.

In the case of a transistor in which W_(T) is as short as the thickness of the oxide semiconductor layer 230 as illustrated in FIG. 4B, an electric field from the gate electrode 270 to the side surface of the oxide semiconductor layer 230 is applied to the entire oxide semiconductor layer 230; thus, a channel is also formed in the side surface of the oxide semiconductor layer 230. Accordingly, the on-state current is expected to be increased by making the oxide semiconductor layer 230 thick, for example. However, in the conventional transistor, the on-state current is not sufficiently increased because carriers are scattered at the interface between a channel formation layer (the oxide semiconductor layer 230) and the gate insulating film 260.

Further, the thickness (T_(GI2)) of the gate insulating film 260 which covers the side surface of the oxide semiconductor layer 230 is likely to be smaller than the thickness (T_(GI1)) of the gate insulating film which covers the top surface of the oxide semiconductor layer, depending on the deposition method. Thus, a portion having low withstand voltage is formed in the gate insulating film 260, which might reduce the reliability of the transistor.

In addition, since T_(GI1) and T_(GI2) are different from each other, an electric field applied from the gate electrode 270 to the oxide semiconductor layer 230 varies. Thus, the on-state current might vary.

On the other hand, in the transistor of one embodiment of the present invention, the third oxide semiconductor layer 133 is formed between the gate insulating film 160 and the second oxide semiconductor layer 132 where a channel is formed, as described above. Accordingly, scattering of carriers at the interface between the channel formation layer and the gate insulating film can be reduced and the field-effect mobility of the transistor can be increased.

Further, in the transistor of one embodiment of the present invention, the third oxide semiconductor layer 133 is formed so as to cover the second oxide semiconductor layer 132 where a channel is formed; thus, scattering of carriers in a side surface of the second oxide semiconductor layer 132 can be reduced as in the top surface. This means that the on-state current of the transistor of one embodiment of the present invention can be higher than that of the conventional transistor.

In particular, the electrical characteristics of the transistor of one embodiment of the present invention are highly improved with a structure in which W_(T) is as small as or smaller than the thickness of the second oxide semiconductor layer 132, as in a cross section of the transistor 100 in the channel width direction illustrated in FIG. 5A or FIG. 5B and in a cross section of the transistor 101 in the channel width direction illustrated in FIG. 17A or FIG. 17B.

In the case of any of the transistors illustrated in FIGS. 5A and 5B and FIGS. 17A and 17B, an electric field from the gate electrode layer 170 to a side surface of the second oxide semiconductor layer 132 is applied to the entire second oxide semiconductor layer 132; thus, a channel is formed equally in the side and top surfaces of the second oxide semiconductor layer 132.

The transistor of one embodiment of the present invention has a structure in which an electric field is easily applied from the gate electrode layer 170 to the side surface of the second oxide semiconductor layer 132. In particular, in the first oxide semiconductor layer 131 of the transistor 101, a region not overlapping with the second oxide semiconductor layer 132 is thinner than a region overlapping with the second oxide semiconductor layer 132. Accordingly, the side surface of the second oxide semiconductor layer 132 where a channel is formed is easily covered by the gate electrode layer 170 with the gate insulating film 160 and the third oxide semiconductor layer 133 provided between the second oxide semiconductor layer 132 and the gate electrode layer 170. As a result, an electric field from the gate electrode layer 170 is likely to be applied to the entire second oxide semiconductor layer 132.

In the case where a channel region 137 as in FIG. 5A and FIG. 17A is formed in the transistor, the channel width can be defined as the sum of W_(T), W_(S1), and W_(S2), and on-state current flows in the transistor in accordance with the channel width.

In the case of a transistor with an extremely small W_(T) as illustrated in FIG. 5B and FIG. 17B, a channel region 138 is formed entirely in the second oxide semiconductor layer 132 in the W_(T) direction, in some cases. In this case, current flows in the entire second oxide semiconductor layer 132; thus, extremely high on-state current flows in the transistor. In the case where W_(T) and W_(S1) of the transistor illustrated in FIG. 5A or FIG. 17A are sufficiently small, current flows in the entire second oxide semiconductor layer 132.

One feature of the transistor of one embodiment of the present invention is that T_(GI1) and T_(GI2) of the gate insulating film 160 are substantially equal. In such a case, an electric field applied from the gate electrode layer 170 to the second oxide semiconductor layer 132 does not vary and a channel is formed uniformly in the top surface and the side surface of the second oxide semiconductor layer 132. Thus, in the case where W_(S1) and W_(S2) are equal to W_(T), on-state current can be approximately three times as high as that in the case where a channel is formed only in the top surface. In the case where W_(S1) and W_(S2) are each twice as long as W_(T) as in a cross section of the transistor 100 in the channel width direction in FIG. 6 and a cross section of the transistor 101 in the channel width direction in FIG. 18, on-state current can be approximately five times as high as that in the case where a channel is formed only in the top surface.

Since T_(GI1) and T_(GI2) of the gate insulating film 160 of the transistor of one embodiment of the present invention are substantially equal, a portion having low withstand voltage is not formed in the gate insulating film 260 and a highly reliable transistor can be formed.

Note that in order to efficiently increase the on-state current of the transistor when W_(S1) and W_(S2) are represented by W_(S), a relation 0.3W_(S)≦W_(T)≦3W_(S) (W_(T) is greater than or equal to 0.3W_(S) and less than or equal to 3W_(S)) is satisfied. Further, W_(T)/W_(S) is preferably greater than or equal to 0.5 and less than or equal to 1.5, further preferably greater than or equal to 0.7 and less than or equal to 1.3. In the case where W_(T)/W_(S)>3, the S value and the off-state current might be increased.

As described above, with the transistor of one embodiment of the present invention, sufficiently high on-state current can be obtained even when the transistor is miniaturized.

In the transistor of one embodiment of the present invention, the second oxide semiconductor layer 132 is formed over the first oxide semiconductor layer 131, so that an interface state is less likely to be formed. In addition, impurities do not enter the second oxide semiconductor layer 132 from above and below because the second oxide semiconductor layer 132 is an intermediate layer in a three-layer structure. Since the second oxide semiconductor layer 132 is surrounded by the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133, not only can the on-state current of the transistor be increased but also the threshold voltage can be stabilized and the S value can be improved. Thus, Icut (current when gate voltage VG is 0 V) can be reduced and power consumption can be reduced. Further, the threshold voltage of the transistor becomes stable; thus, long-term reliability of the semiconductor device can be improved.

The transistor of one embodiment of the present invention may include a conductive film 172 between the base insulating film 120 and the substrate 110 as illustrated in FIG. 7 and FIG. 19. When the conductive film is used as a second gate electrode, the on-state current can be further increased and the threshold voltage can be controlled. In order to increase the on-state current, for example, the gate electrode layer 170 and the conductive film 172 are set to have the same potential, and the transistor is driven as a dual-gate transistor. Further, to control the threshold voltage, a fixed potential, which is different from a potential of the gate electrode layer 170, is supplied to the conductive film 172.

This embodiment can be combined as appropriate with any of the other embodiments in this specification.

(Embodiment 2)

In this embodiment, a method for forming the transistor 100, which is described in Embodiment 1 with reference to FIGS. 1A to 1D, is described with reference to FIGS. 8A to 8C and FIGS. 9A to 9C.

For the substrate 110, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. Alternatively, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, or the like, a compound semiconductor substrate made of silicon germanium or the like, a silicon-on-insulator (SOI) substrate, or the like can be used. Still alternatively, any of these substrates further provided with a semiconductor element can be used.

The base insulating film 120 can be formed by a plasma CVD method, a sputtering method, or the like using an oxide insulating film of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or the like; a nitride insulating film of silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like; or a film in which any of the above materials are mixed. Alternatively, a stack including any of the above materials may be used, and at least an upper layer of the base insulating film 120 which is in contact with the oxide semiconductor layer 130 is preferably formed using a material containing excess oxygen that might serve as a supply source of oxygen to the oxide semiconductor layer 130.

Oxygen may be added to the base insulating film 120 by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like. Adding oxygen enables the base insulating film 120 to supply oxygen much easily to the oxide semiconductor layer 130.

In the case where a surface of the substrate 110 is made of an insulator and there is no influence of impurity diffusion to the oxide semiconductor layer 130 to be formed later, the base insulating film 120 is not necessarily provided.

Next, a first oxide semiconductor film 331 to be the first oxide semiconductor layer 131 is deposited over the base insulating film 120 by a sputtering method, a chemical vapor deposition (CVD) method, an MBE method, an atomic layer deposition (ALD) method, or a PLD method (see FIG. 8A).

Subsequently, a second oxide semiconductor film is deposited over the first oxide semiconductor film 331 by a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method. Then, the second oxide semiconductor film is selectively etched to form the second oxide semiconductor layer 132 (see FIG. 8B).

In order to form a continuous energy band in a stack including the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 or a stack including the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133, which is formed in a later step, the layers need to be stacked successively without exposure to the air with the use of a multi-chamber deposition apparatus (e.g., a sputtering apparatus) including a load lock chamber. It is preferable that each chamber of the sputtering apparatus be able to be evacuated to a high vacuum (to about 5×10⁻⁷ Pa to 1×10⁻⁴ Pa) by an adsorption vacuum pump such as a cryopump and that the chamber be able to heat a substrate over which a film is to be deposited to 100° C. or higher, preferably 500° C. or higher, so that water and the like acting as impurities of an oxide semiconductor are removed as much as possible. Alternatively, a combination of a turbo molecular pump and a cold trap is preferably used to prevent back-flow of a gas containing a carbon component, moisture, or the like from an exhaust system into the chamber.

Not only high vacuum evaporation of the chamber but also high purity of a sputtering gas is necessary to obtain a highly purified intrinsic oxide semiconductor. As an oxygen gas or an argon gas used as the sputtering gas, a gas that is highly purified to have a dew point of −40° C. or lower, preferably −80° C. or lower, further preferably −100° C. or lower is used, so that entry of moisture and the like into the oxide semiconductor layer can be prevented as much as possible.

For the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133 formed in a later step, any of the materials described in Embodiment 1 can be used. For example, an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:3:6, 1:3:4, 1:3:3, or 1:3:2 can be used for the first oxide semiconductor layer 131, an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:1:1 or 5:5:6 can be used for the second oxide semiconductor layer 132, and an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:3:6, 1:3:4, 1:3:3, or 1:3:2 can be used for the third oxide semiconductor layer 133.

An oxide semiconductor that can be used for each of the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133 preferably contains at least indium (In) or zinc (Zn). Alternatively, the oxide semiconductor preferably contains both In and Zn. In order to reduce variation in electrical characteristics of the transistor including the oxide semiconductor, the oxide semiconductor preferably contains a stabilizer in addition to In and/or Zn.

Examples of a stabilizer include gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), and zirconium (Zr). Other example of a stabilizer are lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

As the oxide semiconductor, for example, any of the following can be used: indium oxide, tin oxide, zinc oxide, an In—Zn oxide, a Sn—Zn oxide, an Al—Zn oxide, a Zn—Mg oxide, a Sn—Mg oxide, an In—Mg oxide, an In—Ga oxide, an In—Ga—Zn oxide, an In—Al—Zn oxide, an In—Sn—Zn oxide, a Sn—Ga—Zn oxide, an Al—Ga—Zn oxide, a Sn—Al—Zn oxide, an In—Hf—Zn oxide, an In—La—Zn oxide, an In—Ce—Zn oxide, an In—Pr—Zn oxide, an In—Nd—Zn oxide, an In—Sm—Zn oxide, an In—Eu—Zn oxide, an In—Gd—Zn oxide, an In—Tb—Zn oxide, an In—Dy—Zn oxide, an In—Ho—Zn oxide, an In—Er—Zn oxide, an In—Tm—Zn oxide, an In—Yb—Zn oxide, an In—Lu—Zn oxide, an In—Sn—Ga—Zn oxide, an In—Hf—Ga—Zn oxide, an In—Al—Ga—Zn oxide, an In—Sn—Al—Zn oxide, an In—Sn—Hf—Zn oxide, and an In—Hf—Al—Zn oxide.

Note that here, for example, an “In—Ga—Zn oxide” means an oxide containing In, Ga, and Zn as its main components. The In—Ga—Zn oxide may contain a metal element other than In, Ga, and Zn. Further, in this specification, a film formed using an In—Ga—Zn oxide is also referred to as an IGZO film.

Alternatively, a material represented by InMO₃(ZnO)_(m) (m>0, where m is not an integer) may be used. Note that M represents one or more metal elements selected from Ga, Fe, Mn, Co, Y, Zr, La, Ce, and Nd. Further alternatively, a material represented by In₂SnO₅(ZnO)_(n) (n>0, where n is an integer) may be used.

Note that as described in Embodiment 1 in detail, a material of the second oxide semiconductor layer 132 is selected so that the second oxide semiconductor layer 132 has an electron affinity higher than that of the first oxide semiconductor layer 131 and that of the third oxide semiconductor layer 133.

Note that the oxide semiconductor layers are each preferably formed by a sputtering method. As a sputtering method, an RF sputtering method, a DC sputtering method, an AC sputtering method, or the like can be used. In particular, a DC sputtering method is preferably used because dust generated in the deposition can be reduced and the film thickness can be uniform.

In the case where an In—Ga—Zn oxide is used for the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, or the third oxide semiconductor layer 133, a material whose atomic ratio of In to Ga and Zn is any of 1:1:1, 2:2:1, 3:1:2, 5:5:6, 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:3, 1:5:4, 1:6:6, 2:1:3, 1:6:4, 1:9:6, 1:1:4, and 1:1:2 can be used.

Note that for example, in the case where the composition of an oxide containing In, Ga, and Zn at the atomic ratio, In:Ga:Zn=a:b:c (a+b+c=1), is in the neighborhood of the composition of an oxide containing In, Ga, and Zn at the atomic ratio, In:Ga:Zn=A:B:C (A+B+C=1), a, b, and c satisfy the following relation: (a−A)²+(b−B)²+(c−C)²≦r², and r may be 0.05, for example. The same applies to other oxides.

The indium content of the second oxide semiconductor layer 132 is preferably higher than the indium content of the first oxide semiconductor layer 131 and the indium content of the third oxide semiconductor layer 133. In an oxide semiconductor, the s orbital of heavy metal mainly contributes to carrier transfer, and when the proportion of In in the oxide semiconductor is increased, overlap of the s orbitals is likely to be increased. Thus, an oxide having a composition in which the proportion of In is higher than that of Ga has higher mobility than an oxide having a composition in which the proportion of In is equal to or lower than that of Ga. For this reason, with the use of an oxide having a high indium content for the second oxide semiconductor layer 132, a transistor having high mobility can be achieved.

A structure of an oxide semiconductor film is described below.

Note that in this specification, a term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. In addition, a term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly includes the case where the angle is greater than or equal to 85° and less than or equal to 95°.

In this specification, the trigonal and rhombohedral crystal systems are included in the hexagonal crystal system.

An oxide semiconductor film is classified roughly into a single-crystal oxide semiconductor film and a non-single-crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film includes any of a c-axis aligned crystalline oxide semiconductor (CAAC-OS) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

First, a CAAC-OS film is described.

The CAAC-OS film is one of oxide semiconductor films including a plurality of crystal parts, and most of the crystal parts each fit inside a cube whose one side is less than 100 nm. Thus, there is a case where a crystal part included in the CAAC-OS film fits inside a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm.

In a transmission electron microscope (TEM) image of the CAAC-OS film, a boundary between crystal parts, that is, a grain boundary is not clearly observed. Thus, in the CAAC-OS film, a reduction in electron mobility due to the grain boundary is less likely to occur.

According to the TEM image of the CAAC-OS film observed in a direction substantially parallel to a sample surface (cross-sectional TEM image), metal atoms are arranged in a layered manner in the crystal parts. Each metal atom layer has a morphology reflected by a surface over which the CAAC-OS film is formed (hereinafter, a surface over which the CAAC-OS film is formed is referred to as a formation surface) or a top surface of the CAAC-OS film, and is arranged in parallel to the formation surface or the top surface of the CAAC-OS film.

On the other hand, according to the TEM image of the CAAC-OS film observed in a direction substantially perpendicular to the sample surface (plan TEM image), metal atoms are arranged in a triangular or hexagonal configuration in the crystal parts. However, there is no regularity of arrangement of metal atoms between different crystal parts.

From the results of the cross-sectional TEM image and the plan TEM image, alignment is found in the crystal parts in the CAAC-OS film.

A CAAC-OS film is subjected to structural analysis with an X-ray diffraction (XRD) apparatus. For example, when the CAAC-OS film including an InGaZnO₄ crystal is analyzed by an out-of-plane method, a peak appears frequently when the diffraction angle (2θ) is around 31°. This peak is derived from the (009) plane of the InGaZnO₄ crystal, which indicates that crystals in the CAAC-OS film have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS film.

On the other hand, when the CAAC-OS film is analyzed by an in-plane method in which an X-ray enters a sample in a direction substantially perpendicular to the c-axis, a peak appears frequently when 2θ is around 56°. This peak is derived from the (110) plane of the InGaZnO₄ crystal. Here, analysis (φ scan) is performed under conditions where the sample is rotated around a normal vector of a sample surface as an axis (φ axis) with 2θ fixed at around 56°. In the case where the sample is a single-crystal oxide semiconductor film of InGaZnO₄, six peaks appear. The six peaks are derived from crystal planes equivalent to the (110) plane. On the other hand, in the case of a CAAC-OS film, a peak is not clearly observed even when φ scan is performed with 2θ fixed at around 56°.

According to the above results, in the CAAC-OS film having c-axis alignment, while the directions of a-axes and b-axes are different between crystal parts, the c-axes are aligned in a direction parallel to a normal vector of a formation surface or a normal vector of a top surface. Thus, each metal atom layer arranged in a layered manner observed in the cross-sectional TEM image corresponds to a plane parallel to the a-b plane of the crystal.

Note that the crystal part is formed concurrently with deposition of the CAAC-OS film or is formed through crystallization treatment such as heat treatment. As described above, the c-axes of the crystal are aligned in a direction parallel to a normal vector of a formation surface or a normal vector of a top surface. Thus, for example, in the case where a shape of the CAAC-OS film is changed by etching or the like, the c-axis might not be necessarily parallel to a normal vector of a formation surface or a normal vector of a top surface of the CAAC-OS film.

Further, the degree of crystallinity in the CAAC-OS film is not necessarily uniform. For example, in the case where crystal growth leading to the CAAC-OS film occurs from the vicinity of the top surface of the film, the degree of the crystallinity in the vicinity of the top surface is higher than that in the vicinity of the formation surface in some cases. Further, when an impurity is added to the CAAC-OS film, the crystallinity in a region to which the impurity is added is changed, and the degree of crystallinity in the CAAC-OS film varies depending on regions.

Note that when the CAAC-OS film with an InGaZnO₄ crystal is analyzed by an out-of-plane method, a peak of 2θ may also be observed at around 36°, in addition to the peak of 2θ at around 31°. The peak of 2θ at around 36° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. It is preferable that in the CAAC-OS film, a peak of 2θ appear at around 31° and a peak of 2θ do not appear at around 36°.

The CAAC-OS film is an oxide semiconductor film having low impurity concentration. The impurity is an element other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, or a transition metal element. In particular, an element that has higher bonding strength to oxygen than a metal element included in the oxide semiconductor film, such as silicon, disturbs the atomic arrangement of the oxide semiconductor film by depriving the oxide semiconductor film of oxygen and causes a decrease in crystallinity. Further, a heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor film and causes a decrease in crystallinity when it is contained in the oxide semiconductor film. Note that the impurity contained in the oxide semiconductor film might serve as a carrier trap or a carrier generation source.

Further, the CAAC-OS film is an oxide semiconductor film having a low density of defect states. For example, an oxygen vacancy in the oxide semiconductor film serves as a carrier trap or a carrier generation source in some cases when hydrogen is captured therein.

The state in which the impurity concentration is low and the density of defect states is low (the number of oxygen vacancies is small) is referred to as a highly purified intrinsic state or a substantially highly purified intrinsic state. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. Thus, a transistor including the oxide semiconductor film rarely has negative threshold voltage (is rarely normally on). The highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier traps. Accordingly, the transistor including the oxide semiconductor film has small variations in electrical characteristics and high reliability. Electric charge trapped by the carrier traps in the oxide semiconductor film takes a long time to be released, and might behave like fixed electric charge. Thus, the transistor that includes the oxide semiconductor film having high impurity concentration and a high density of defect states has unstable electrical characteristics in some cases.

With the use of the CAAC-OS film in a transistor, variation in the electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light is small.

Next, a microcrystalline oxide semiconductor film is described.

In an image obtained with a TEM, crystal parts cannot be found clearly in the microcrystalline oxide semiconductor in some cases. In most cases, the size of a crystal part in the microcrystalline oxide semiconductor film is greater than or equal to 1 nm and less than or equal to 100 nm, or greater than or equal to 1 nm and less than or equal to 10 nm. An oxide semiconductor film including a nanocrystal (nc), which is a microcrystal with a size greater than or equal to 1 nm and less than or equal to 10 nm, or a size greater than or equal to 1 nm and less than or equal to 3 nm, is specifically referred to as a nanocrystalline oxide semiconductor (nc-OS) film. In an image of the nc-OS film obtained with a TEM, for example, a crystal grain cannot be observed clearly in some cases.

In the nc-OS film, a microscopic region (e.g., a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic order. Further, there is no regularity of crystal orientation between different crystal parts in the nc-OS film; thus, the orientation of the whole film is not observed. Accordingly, in some cases, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on an analysis method. For example, when the nc-OS film is subjected to structural analysis by an out-of-plane method with an XRD apparatus using an X-ray having a diameter larger than that of a crystal part, a peak which shows a crystal plane does not appear. Further, a halo pattern is shown in an electron diffraction pattern (also referred to as a selected-area electron diffraction pattern) of the nc-OS film obtained by using an electron beam having a probe diameter (e.g., larger than or equal to 50 nm) larger than the diameter of a crystal part. Meanwhile, spots are shown in a nanobeam electron diffraction pattern of the nc-OS film obtained by using an electron beam having a probe diameter (e.g., larger than or equal to 1 nm and smaller than or equal to 30 nm) close to, or smaller than or equal to the diameter of a crystal part. In some cases, in a nanobeam electron diffraction pattern of the nc-OS film, regions with high luminance in a circular (ring) pattern are shown. Further, in a nanobeam electron diffraction pattern of the nc-OS film, a plurality of spots are shown in a ring-like region in some cases.

Since an nc-OS film is an oxide semiconductor film having more regularity than an amorphous oxide semiconductor film, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. However, there is no regularity of crystal orientation between different crystal parts in the nc-OS film; hence, the nc-OS film has a higher density of defect states than a CAAC-OS film.

Note that an oxide semiconductor film may be a stacked film including two or more films of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.

A CAAC-OS film can be deposited by sputtering with a polycrystalline oxide semiconductor sputtering target, for example. When ions collide with the sputtering target, a crystal region included in the sputtering target may be separated from the target along the a-b plane; in other words, a sputtered particle having a plane parallel to the a-b plane (a flat-plate-like sputtered particle or a pellet-like sputtered particle) might be flake off from the sputtering target. In this case, the flat-plate-like sputtered particle or the pellet-like sputtered particle is electrically charged and thus reaches a substrate while maintaining its crystal state without being aggregated in plasma, whereby a CAAC-OS film can be formed.

In the case where the second oxide semiconductor layer 132 is formed using an In—M—Zn oxide (M is Ga, Y, Zr, La, Ce, or Nd) and a sputtering target whose atomic ratio of In to M and Zn is a1:b1:c1 is used for forming the second oxide semiconductor layer 132, a1/b1 is preferably greater than or equal to ⅓ and less than or equal to 6, further preferably greater than or equal to 1 and less than or equal to 6, and c1/b1 is preferably greater than or equal to ⅓ and less than or equal to 6, further preferably greater than or equal to 1 and less than or equal to 6. Note that when c1/b1 is greater than or equal to 1 and less than or equal to 6, the second oxide semiconductor layer 132 is easily formed as a CAAC-OS film. Typical examples of the atomic ratio of In to M and Zn of the target are 1:1:1, 3:1:2, and 5:5:6.

In the case where the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are each formed using an In—M—Zn oxide (M is Ga, Y, Zr, La, Ce, or Nd) and a sputtering target whose atomic ratio of In to M and Zn is a2:b2:c2 is used for forming the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133, a2/b2 is preferably less than a1/b1, and c2/b2 is preferably greater than or equal to ⅓ and less than or equal to 6, further preferably greater than or equal to 1 and less than or equal to 6. Note that when c2/b2 is greater than or equal to 1 and less than or equal to 6, CAAC-OS films are easily formed as the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133. Typical examples of the atomic ratio of In to M and Zn of the target are 1:3:2, 1:3:3, 1:3:4, and 1:3:6.

Here, an example of a crystal structure of the oxide semiconductor layer 130 in the transistor of one embodiment of the present invention is described with reference to FIGS. 10A to 10D.

FIG. 10A is a cross-sectional view of the transistor of one embodiment of the present invention in the channel width direction. FIG. 10B is an enlarged view of a region 400 included in the oxide semiconductor layer 130 illustrated in FIG. 10A.

Lateral dotted lines in FIG. 10B schematically show a layered structure of a crystal. In a crystal in the first oxide semiconductor layer 131, c-axes are aligned in a direction substantially perpendicular to the interface with the base insulating film 120. It is preferable that c-axes of the crystals in the second oxide semiconductor layer 132 and the third oxide semiconductor layer 133 formed over the first oxide semiconductor layer 131 be aligned in the same direction as those in the first oxide semiconductor layer 131.

It is also preferable that crystals be connected in a region 410 where the second oxide semiconductor layer 132 and the third oxide semiconductor layer 133 are in contact with each other. As illustrated in FIG. 10C, an In—Ga—Zn oxide has a crystal structure in which two kinds of layers, a layer of InO₂ and a layer of an oxide containing Ga or Zn ((Ga, Zn)O), are arranged in a layered manner in the c-axis direction.

At the time of deposition of the third oxide semiconductor layer 133, owing to InO₂ contained in the above-described flat-plate-like sputtered particle or pellet-shaped sputtered particle, crystals are connected in the region 410 where the second oxide semiconductor layer 132 and the third oxide semiconductor layer 133 are in contact with each other, as illustrated in FIG. 10D.

The crystal connection can suppress formation of a defect level such as a trap center or a recombination center at the interface between the second oxide semiconductor layer 132 and the third oxide semiconductor layer 133. Although InO₂ molecules contained in the second oxide semiconductor layer 132 and the third oxide semiconductor layer 133 are connected linearly in FIG. 10D, one embodiment of the present invention is not limited thereto and can have a structure in which InO₂ molecules positioned at different heights are connected to each other.

First heat treatment may be performed after the second oxide semiconductor layer 132 is formed. The first heat treatment may be performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C., in an inert gas atmosphere, in an atmosphere containing an oxidizing gas at 10 ppm or more, or under reduced pressure. Alternatively, the first heat treatment may be performed in such a manner that heat treatment is performed in an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more in order to compensate desorbed oxygen. By the first heat treatment, the crystallinity of the second oxide semiconductor layer 132 can be improved, and in addition, impurities such as hydrogen and water can be removed from the base insulating film 120 and the first oxide semiconductor layer 131. Note that the first heat treatment may be performed before etching for formation of the second oxide semiconductor layer 132.

Next, a first conductive film to be the source electrode layer 140 and the drain electrode layer 150 is formed over the first oxide semiconductor film 331 and the second oxide semiconductor layer 132. For the first conductive film, Al, Cr, Cu, Ta, Ti, Mo, W, or an alloy material containing any of these as its main component can be used. For example, a 100-nm-thick titanium film is formed by a sputtering method or the like. Alternatively, a tungsten film may be formed by a CVD method.

Next, the first conductive film is etched so as to be divided over the second oxide semiconductor layer 132 to form the source electrode layer 140 and the drain electrode layer 150 (see FIG. 8C). At this time, the first conductive film may be over-etched, so that the second oxide semiconductor layer 132 is partly etched.

Subsequently, a third oxide semiconductor film 333 to be the third oxide semiconductor layer 133 is formed over the first oxide semiconductor film 331, the second oxide semiconductor layer 132, the source electrode layer 140, and the drain electrode layer 150.

Note that second heat treatment may be performed after the third oxide semiconductor film 333 is formed. The second heat treatment can be performed under the conditions similar to those of the first heat treatment. The second heat treatment can remove impurities such as hydrogen and water from the third oxide semiconductor film 333, the first oxide semiconductor film 331, and the second oxide semiconductor layer 132.

The first oxide semiconductor film 331 entirely covers the base insulating film 120 at the time of the first heat treatment, deposition of the first conductive film, and the second heat treatment. Although the heat treatment and deposition of the conductive film by the CVD method are performed at high temperature, the first oxide semiconductor film entirely covering the base insulating film 120 can prevent unnecessary release of excess oxygen contained in the base insulating film 120.

Next, an insulating film 360 to be the gate insulating film 160 is formed over the third oxide semiconductor film 333. The insulating film 360 can be formed using aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or the like. The insulating film 360 may be a stack including any of the above materials. The insulating film 360 can be formed by a sputtering method, a CVD method, an MBE method, an ALD method, a PLD method, or the like. It is preferable to form the gate insulating film 160 by selecting a raw material, temperature, pressure, the distance between electrodes, applied power, and the like so that the coverage can be improved and T_(GI1) and T_(GI2) are substantially equal to each other as illustrated in FIG. 5A. For example, the coverage can be improved by deposition under the conditions of high temperature and high pressure in a range where the film quality as a gate insulating film can be maintained.

Then, a second conductive film 370 to be the gate electrode layer 170 is formed over the insulating film 360 (see FIG. 9A). For the second conductive film 370, Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Ta, W, or an alloy material containing any of these as its main component can be used. The second conductive film 370 can be formed by a sputtering method, a CVD method, or the like. A stack including a conductive film containing any of the above materials and a conductive film containing nitrogen, or a conductive film containing nitrogen may be used for the second conductive film 370.

After that, the second conductive film 370 is selectively etched using a resist mask to form the gate electrode layer 170.

Then, the insulating film 360 is selectively etched using the resist mask or the gate electrode layer 170 as a mask to form the gate insulating film 160.

Subsequently, the third oxide semiconductor film 333 is etched using the resist mask or the gate electrode layer 170 as a mask to form the third oxide semiconductor layer 133.

After that, the first oxide semiconductor film 331 is selectively etched using the resist mask or the gate electrode layer 170, the source electrode layer 140, and the drain electrode layer 150 as a mask to form the first oxide semiconductor layer 131 (see FIG. 9B).

The second conductive film 370, the insulating film 360, the third oxide semiconductor film 333, and the first oxide semiconductor film 331 may be etched individually or successively.

Next, the oxide insulating layer 180 is formed over the source electrode layer 140, the drain electrode layer 150, and the gate electrode layer 170 (see FIG. 9C). The oxide insulating layer 180 can be formed using a material and a method which are similar to those of the base insulating film 120.

Oxygen may be added to the oxide insulating layer 180 by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like. Adding oxygen enables the oxide insulating layer 180 to supply oxygen much easily to the oxide semiconductor layer 130.

Next, third heat treatment may be performed. The third heat treatment can be performed under conditions similar to those of the first heat treatment. By the third heat treatment, excess oxygen is easily released from the base insulating film 120, the gate insulating film 160, and the oxide insulating layer 180, so that oxygen vacancies in the oxide semiconductor layer 130 can be reduced.

Through the above process, the transistor 100 illustrated in FIGS. 1A to 1D can be formed.

The transistor 101 can be manufactured in a process similar to that of the transistor 100 (see FIGS. 20A to 20C and FIGS. 21A to 21C). Note that the first oxide semiconductor film 331 is overetched so that the thickness (T_(OS2)) of a region not overlapping with the second oxide semiconductor layer 132 is smaller than the thickness (T_(OS1)) of a region overlapping with the second oxide semiconductor layer 132 in the first oxide semiconductor film 331 as illustrated in FIG. 20B. For example, T_(OS2)/T_(OS1) is made greater than or equal to 0.1 and less than or equal to 0.8, preferably greater than or equal to 0.1 and less than or equal to 0.5, further preferably greater than or equal to 0.1 and less than or equal to 0.3.

Various films such as the metal film described in this embodiment can be formed typically by a sputtering method or a plasma CVD method; however, these films may be formed by another method such as a thermal CVD method. A metal organic chemical vapor deposition (MOCVD) method and an ALD method are given as examples of a thermal CVD method.

A thermal CVD method has an advantage that no defect due to plasma damage is generated since it does not utilize plasma for forming a film.

Deposition by a thermal CVD method may be performed in such a manner that a source gas and an oxidizer are supplied to the chamber at a time, the pressure in a chamber is set to an atmospheric pressure or a reduced pressure, and reaction is caused in the vicinity of the substrate or over the substrate.

Deposition by an ALD method may be performed in such a manner that the pressure in a chamber is set to an atmospheric pressure or a reduced pressure, source gases for reaction are sequentially introduced into the chamber, and then the sequence of the gas introduction is repeated. For example, two or more kinds of source gases are sequentially supplied to the chamber by switching respective switching valves (also referred to as high-speed valves). In such a case, a first source gas is introduced, an inert gas (e.g., argon or nitrogen) or the like is introduced at the same time as or after the first gas is introduced, and then a second source gas is introduced, whereby the source gases are not mixed. Note that in the case where the first source gas and the inert gas are introduced at a time, the inert gas serves as a carrier gas, and the inert gas may also be introduced at the same time as the second source gas. Instead of the introduction of the inert gas, the first source gas may be exhausted by vacuum evacuation, and then the second source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first layer and then, the second source gas is introduced to react with the first layer; as a result, a second layer is stacked over the first layer, so that a thin film is formed. The sequence of the gas introduction is repeated plural times until a desired thickness is obtained, whereby a thin film with excellent step coverage can be formed. The thickness of the thin film can be adjusted by the number of repetition times of the sequence of the gas introduction; therefore, an ALD method makes it possible to accurately adjust a thickness and thus is suitable for manufacturing a minute FET.

For example, in the case where a tungsten film is formed using a deposition apparatus employing ALD, a WF₆ gas and a B₂H₆ gas are sequentially introduced plural times to form an initial tungsten film, and then a WF₆ gas and an H₂ gas are introduced at a time, so that a tungsten film is formed. Note that an SiH₄ gas may be used instead of a B₂H₆ gas.

This embodiment can be combined as appropriate with any of the other embodiments in this specification.

(Embodiment 3)

In this embodiment, an example of a semiconductor device (storage device) which includes a transistor of one embodiment of the present invention, which can retain stored data even when not powered, and which has an unlimited number of write cycles is described with reference to drawings.

FIG. 11A is a cross-sectional view of the semiconductor device, and FIG. 11B is a circuit diagram of the semiconductor device.

The semiconductor device illustrated in FIGS. 11A and 11B includes a transistor 3200 including a first semiconductor material in a lower portion, and a transistor 3300 including a second semiconductor material and a capacitor 3400 in an upper portion. Note that the transistor 100 or the transistor 101 described in Embodiment 1 can be used as the transistor 3300.

One electrode of the capacitor 3400 is formed using the same material as a source electrode layer and a drain electrode layer of the transistor 3300, the other electrode of the capacitor 3400 is formed using the same material as a gate electrode layer of the transistor 3300, and a dielectric of the capacitor 3400 is formed using the same material as the third oxide semiconductor layer and the gate insulating film 160 of the transistor 3300; thus, the capacitor 3400 can be formed at the same time as the transistor 3300.

Here, the first semiconductor material and the second semiconductor material are preferably materials having different band gaps. For example, the first semiconductor material may be a semiconductor material (such as silicon) other than an oxide semiconductor, and the second semiconductor material may be the oxide semiconductor described in Embodiment 1. A transistor including a material other than an oxide semiconductor can operate at high speed easily. On the other hand, a transistor including an oxide semiconductor enables charge to be retained for a long time owing to its electrical characteristics, that is, the low off-state current.

Although both of the above transistors are n-channel transistors in the following description, it is needless to say that p-channel transistors can be used. The specific structure of the semiconductor device, such as a material used for the semiconductor device and the structure of the semiconductor device, needs not to be limited to that described here except for the use of the transistor described in Embodiment 1, which is formed using an oxide semiconductor. for retaining data.

The transistor 3200 in FIG. 11A includes a channel formation region provided in a substrate 3000 including a semiconductor material (such as crystalline silicon), impurity regions provided such that the channel formation region is provided therebetween, intermetallic compound regions provided in contact with the impurity regions, a gate insulating film provided over the channel formation region, and a gate electrode layer provided over the gate insulating film. Note that a transistor whose source electrode layer and drain electrode layer are not illustrated in a drawing may also be referred to as a transistor for the sake of convenience. Further, in such a case, in description of a connection of a transistor, a source region and a source electrode layer may be collectively referred to as a source electrode layer, and a drain region and a drain electrode layer may be collectively referred to as a drain electrode layer. That is, in this specification, the term “source electrode layer” might include a source region.

Further, an element isolation insulating layer 3100 is formed on the substrate 3000 so as to surround the transistor 3200, and an insulating layer 3150 is formed so as to cover the transistor 3200. Note that the element isolation insulating layer 3100 can be formed by an element isolation technique such as local oxidation of silicon (LOCOS) or shallow trench isolation (STI).

For example, in the case where the transistor 3200 is formed using a crystalline silicon substrate, the transistor 3200 can operate at high speed. Thus, when the transistor is used as a reading transistor, data can be read at high speed.

The transistor 3300 is provided over the insulating layer 3150, and one of the source electrode layer and the drain electrode layer of the transistor 3300 is extended so as to function as the one electrode of the capacitor 3400. Further, the one electrode of the capacitor 3400 is electrically connected to the gate electrode layer of the transistor 3200 through a connection wiring 3350.

The transistor 3300 in FIG. 11A is a top-gate transistor in which a channel is formed in an oxide semiconductor layer. Since the off-state current of the transistor 3300 is low, stored data can be retained for a long period owing to such a transistor. In other words, refresh operation becomes unnecessary or the frequency of the refresh operation in a semiconductor storage device can be extremely low, which leads to a sufficient reduction in power consumption.

Further, an electrode 3250 overlaps with the transistor 3300 with the insulating layer 3150 provided therebetween. By supplying an appropriate potential to the electrode 3250 and the electrode 3250 is used as a second gate electrode, the threshold voltage of the transistor 3300 can be controlled. In addition, long-term reliability of the transistor 3300 can be improved. When the electrode operates with the same potential as that of the gate electrode of the transistor 3300, on-state current can be increased. Note that the electrode 3250 is not necessarily provided.

The transistor 3300 and the capacitor 3400 can be formed over the substrate over which the transistor 3200 is formed as illustrated in FIG. 11A, which enables the degree of the integration of the semiconductor device to be increased.

An example of a circuit configuration corresponding to FIG. 11A is illustrated in FIG. 11B.

In FIG. 11B, a first wiring 3001 is electrically connected to a source electrode layer of the transistor 3200. A second wiring 3002 is electrically connected to a drain electrode layer of the transistor 3200. A third wiring 3003 is electrically connected to one of the source electrode layer and the drain electrode layer of the transistor 3300. A fourth wiring 3004 is electrically connected to the gate electrode layer of the transistor 3300. The gate electrode layer of the transistor 3200 and the other of the source electrode layer and the drain electrode layer of the transistor 3300 are electrically connected to the one electrode of the capacitor 3400. A fifth wiring 3005 is electrically connected to the other electrode of the capacitor 3400. Note that a component corresponding to the electrode 3250 is not illustrated.

The semiconductor device in FIG. 11B utilizes a characteristic in which the potential of the gate electrode layer of the transistor 3200 can be retained, and thus enables writing, retaining, and reading of data as follows.

Writing and retaining of data are described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the gate electrode layer of the transistor 3200 and the capacitor 3400. That is, a predetermined charge is supplied to the gate electrode layer of the transistor 3200 (writing). Here, one of two kinds of charges providing different potential levels (hereinafter referred to as a low-level charge and a high-level charge) is supplied. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off, so that the transistor 3300 is turned off. Thus, the charge supplied to the gate electrode layer of the transistor 3200 is retained (retaining).

Since the off-state current of the transistor 3300 is extremely low, the charge of the gate electrode layer of the transistor 3200 is retained for a long time.

Next, reading of data is described. By supplying an appropriate potential (a reading potential) to the fifth wiring 3005 while supplying a predetermined potential (a constant potential) to the first wiring 3001, the potential of the second wiring 3002 varies depending on the amount of charge retained in the gate electrode layer of the transistor 3200. This is because in general, when the transistor 3200 is an n-channel transistor, an apparent threshold voltage V_(th) _(_) _(H) in the case where the high-level charge is given to the gate electrode layer of the transistor 3200 is lower than an apparent threshold voltage V_(th) _(_) _(L) in the case where the low-level charge is given to the gate electrode layer of the transistor 3200. Here, an apparent threshold voltage refers to the potential of the fifth wiring 3005 which is needed to turn on the transistor 3200. Thus, the potential of the fifth wiring 3005 is set to a potential V₀ which is between V_(th) _(_) _(H) and V_(th) _(_) _(L), whereby charge supplied to the gate electrode layer of the transistor 3200 can be determined. For example, in the case where the high-level charge is supplied in writing, when the potential of the fifth wiring 3005 is V₀ (>V_(th) _(_) _(H)), the transistor 3200 is turned on. In the case where the low-level charge is supplied in writing, even when the potential of the fifth wiring 3005 is V₀ (<V_(th) _(_) _(L)), the transistor 3200 remains off. Thus, the data retained in the gate electrode layer can be read by determining the potential of the second wiring 3002.

Note that in the case where memory cells are arrayed, it is necessary that only data of a desired memory cell be able to be read. The fifth wiring 3005 in the case where data is not read may be supplied with a potential at which the transistor 3200 is turned off regardless of the state of the gate electrode layer, that is, a potential lower than V_(th) _(_) _(H). Alternatively, the fifth wiring 3005 may be supplied with a potential at which the transistor 3200 is turned on regardless of the state of the gate electrode layer, that is, a potential higher than V_(th) _(_) _(L).

When including a transistor having a channel formation region formed using an oxide semiconductor and having an extremely low off-state current, the semiconductor device described in this embodiment can retain stored data for an extremely long period. In other words, refresh operation becomes unnecessary or the frequency of the refresh operation can be extremely low, which leads to a sufficient reduction in power consumption. Moreover, stored data can be retained for a long period even when power is not supplied (note that a potential is preferably fixed).

Further, in the semiconductor device described in this embodiment, high voltage is not needed for writing data and there is no problem of deterioration of elements. For example, unlike in a conventional nonvolatile memory, it is not necessary to inject and extract electrons into and from a floating gate, and thus a problem such as deterioration of a gate insulating film does not arise. That is, the semiconductor device according to the disclosed invention does not have a limitation on the number of times data can be rewritten, which is a problem of a conventional nonvolatile memory, and the reliability thereof is drastically improved. Furthermore, data is written depending on the on state and the off state of the transistor, whereby high-speed operation can be easily achieved.

As described above, a miniaturized and highly-integrated semiconductor device having high electrical characteristics can be provided.

This embodiment can be combined as appropriate with any of the other embodiments in this specification.

(Embodiment 4)

In this embodiment, a semiconductor device including a transistor of one embodiment of the present invention, which can retain stored data even when not powered, which does not have a limitation on the number of write cycles, and which has a structure different from that described in Embodiment 3, is described.

FIG. 12 illustrates an example of a circuit configuration of the semiconductor device. In the semiconductor device, a first wiring 4500 is electrically connected to a source electrode layer of a transistor 4300, a second wiring 4600 is electrically connected to a first gate electrode layer of the transistor 4300, and a drain electrode layer of the transistor 4300 is electrically connected to a first terminal of a capacitor 4400. Note that the transistor 100 described in Embodiment 1 can be used as the transistor 4300 included in the semiconductor device. The first wiring 4500 can serve as a bit line and the second wiring 4600 can serve as a word line.

The semiconductor device (a memory cell 4250) can have a connection mode similar to that of the transistor 3300 and the capacitor 3400 illustrated in FIGS. 11A and 11B. Thus, the capacitor 4400 can be formed through the same process and at the same time as the transistor 4300 in a manner similar to that of the capacitor 3400 described in Embodiment 3.

Next, writing and retaining of data in the semiconductor device (the memory cell 4250) illustrated in FIG. 12 are described.

First, a potential at which the transistor 4300 is turned on is supplied to the second wiring 4600, so that the transistor 4300 is turned on. Accordingly, the potential of the first wiring 4500 is supplied to the first terminal of the capacitor 4400 (writing). After that, the potential of the second wiring 4600 is set to a potential at which the transistor 4300 is turned off, so that the transistor 4300 is turned off. Thus, the potential of the first terminal of the capacitor 4400 is retained (retaining).

In addition, the transistor 4300 including an oxide semiconductor has an extremely low off-state current. For that reason, the potential of the first terminal of the capacitor 4400 (or a charge accumulated in the capacitor 4400) can be retained for an extremely long time by turning off the transistor 4300.

Next, reading of data is described. When the transistor 4300 is turned on, the first wiring 4500 which is in a floating state and the capacitor 4400 are electrically connected to each other, and the charge is redistributed between the first wiring 4500 and the capacitor 4400. As a result, the potential of the first wiring 4500 is changed. The amount of change in potential of the first wiring 4500 varies depending on the potential of the first terminal of the capacitor 4400 (or the charge accumulated in the capacitor 4400).

For example, the potential of the first wiring 4500 after charge redistribution is (C_(B)×V_(B0)+C×V)/(C_(B)+C), where V is the potential of the first terminal of the capacitor 4400, C is the capacitance of the capacitor 4400, C_(B) is the capacitance component of the first wiring 4500, and V_(B0) is the potential of the first wiring 4500 before the charge redistribution. Therefore, it can be found that assuming that the memory cell 4250 is in either of two states in which the potentials of the first terminal of the capacitor 4400 are V₁ and V₀ (V₁>V₀), the potential of the first wiring 4500 in the case of retaining the potential V₁ (=(C_(B)×V_(B0)+C×V₁)/(C_(B)+C)) is higher than the potential of the first wiring 4500 in the case of retaining the potential V₀ (=(C_(B)×V_(B0)+C×V₀)/(C_(B)+C)).

Then, by comparing the potential of the first wiring 4500 with a predetermined potential, data can be read.

As described above, the semiconductor device (the memory cell 4250) illustrated in FIG. 12 can retain charge that is accumulated in the capacitor 4400 for a long time because the off-state current of the transistor 4300 is extremely low. In other words, refresh operation becomes unnecessary or the frequency of the refresh operation can be extremely low, which leads to a sufficient reduction in power consumption. Moreover, stored data can be retained for a long period even when power is not supplied.

A substrate over which a driver circuit for the memory cell 4250 is formed and the memory cell 4250 illustrated in FIG. 12 are preferably stacked. When the memory cell 4250 and the driver circuit are stacked, the size of the semiconductor device can be reduced. Note that there is no limitation on the numbers of the memory cells 4250 and the driver circuits which are stacked.

It is preferable that a semiconductor material of a transistor included in the driver circuit be different from that of the transistor 4300. For example, silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide can be used, and a single crystal semiconductor is preferably used. A transistor formed using such a semiconductor material can operate at higher speed than a transistor formed using an oxide semiconductor and is suitable for the driver circuit for the memory cell 4250.

As described above, a miniaturized and highly-integrated semiconductor device having high electrical characteristics can be provided.

This embodiment can be combined as appropriate with any of the other embodiments in this specification.

(Embodiment 5)

In this embodiment, a CPU in which at least the transistor described in Embodiment 1 can be used and the storage device described in Embodiment 3 is included is described.

FIG. 13 is a block diagram illustrating a configuration example of a CPU at least partly including the transistor 100 described in Embodiment 1.

The CPU illustrated in FIG. 13 includes, over a substrate 1190, an arithmetic logic unit (ALU) 1191, an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198, a rewritable ROM 1199, and an ROM interface 1189. A semiconductor substrate, an SOI substrate, a glass substrate, or the like is used as the substrate 1190. The rewritable ROM 1199 and the ROM interface 1189 may be provided over a separate chip. Needless to say, the CPU in FIG. 13 is just an example in which the configuration has been simplified, and an actual CPU may have various configurations depending on the application. For example, the CPU may have the following configuration: a structure including the CPU illustrated in FIG. 13 or an arithmetic circuit is considered as one core; a plurality of the cores is included; and the cores operate in parallel. The number of bits that the CPU can process in an internal arithmetic circuit or in a data bus can be 8, 16, 32, or 64, for example.

An instruction that is input to the CPU through the bus interface 1198 is input to the instruction decoder 1193 and decoded therein, and then, input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 conduct various controls in accordance with the decoded instruction. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. While the CPU is executing a program, the interrupt controller 1194 judges an interrupt request from an external input/output device or a peripheral circuit on the basis of its priority or a mask state, and processes the request. The register controller 1197 generates an address of the register 1196, and reads/writes data from/to the register 1196 in accordance with the state of the CPU.

The timing controller 1195 generates signals for controlling operation timings of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generator for generating an internal clock signal CLK2 based on a reference clock signal CLK1, and supplies the internal clock signal CLK2 to the above circuits.

In the CPU illustrated in FIG. 13, a memory cell is provided in the register 1196. As the memory cell of the register 1196, the transistor described in the above embodiment can be used.

In the CPU illustrated in FIG. 13, the register controller 1197 selects operation of retaining data in the register 1196 in accordance with an instruction from the ALU 1191. That is, the register controller 1197 selects whether data is retained by a flip-flop or by a capacitor in the memory cell included in the register 1196. When data retaining by the flip-flop is selected, a power supply voltage is supplied to the memory cell in the register 1196. When data retaining by the capacitor is selected, the data is rewritten in the capacitor, and supply of power supply voltage to the memory cell in the register 1196 can be stopped.

FIG. 14 is an example of a circuit diagram of a storage element that can be used as the register 1196. A memory element 700 includes a circuit 701 in which stored data is volatile when power supply is stopped, a circuit 702 in which stored data is nonvolatile when power supply is stopped, a switch 703, a switch 704, a logic element 706, a capacitor 707, and a circuit 720 having a selecting function. The circuit 702 includes a capacitor 708, a transistor 709, and a transistor 710. Note that the memory element 700 may further include another element such as a diode, a resistor, or an inductor, as needed.

Here, the storage device described in Embodiment 3 can be used as the circuit 702. When supply of the power supply voltage to the memory element 700 is stopped, a ground potential (0 V) or a potential at which the transistor 709 in the circuit 702 is turned off continues to be input to a first gate of the transistor 709. For example, the first gate of the transistor 709 is grounded through a load such as a resistor.

An example in which the switch 703 is a transistor 713 having one conductivity type (e.g., an n-channel transistor) and the switch 704 is a transistor 714 having a conductivity type opposite to the one conductivity type (e.g., a p-channel transistor) is described. Here, a first terminal of the switch 703 corresponds to one of a source and a drain of the transistor 713, a second terminal of the switch 703 corresponds to the other of the source and the drain of the transistor 713, and conduction or non-conduction between the first terminal and the second terminal of the switch 703 (i.e., the on/off state of the transistor 713) is selected by a control signal RD input to a gate of the transistor 713. A first terminal of the switch 704 corresponds to one of a source and a drain of the transistor 714, a second terminal of the switch 704 corresponds to the other of the source and the drain of the transistor 714, and conduction or non-conduction between the first terminal and the second terminal of the switch 704 (i.e., the on/off state of the transistor 714) is selected by the control signal RD input to a gate of the transistor 714.

One of a source and a drain of the transistor 709 is electrically connected to one of a pair of electrodes of the capacitor 708 and a gate of the transistor 710. Here, the connection portion is referred to as a node M2. One of a source and a drain of the transistor 710 is electrically connected to a line which can supply a low power supply potential (e.g., a GND line), and the other thereof is electrically connected to the first terminal of the switch 703 (the one of the source and the drain of the transistor 713). The second terminal of the switch 703 (the other of the source and the drain of the transistor 713) is electrically connected to the first terminal of the switch 704 (the one of the source and the drain of the transistor 714). The second terminal of the switch 704 (the other of the source and the drain of the transistor 714) is electrically connected to a line which can supply a power supply potential VDD. The second terminal of the switch 703 (the other of the source and the drain of the transistor 713), the first terminal of the switch 704 (the one of the source and the drain of the transistor 714), an input terminal of the logic element 706, and one of a pair of electrodes of the capacitor 707 are electrically connected to each other. Here, the connection portion is referred to as a node M1. The other of the pair of electrodes of the capacitor 707 can be supplied with a constant potential. For example, the other of the pair of electrodes of the capacitor 707 can be supplied with a low power supply potential (e.g., GND) or a high power supply potential (e.g., VDD). The other of the pair of electrodes of the capacitor 707 is electrically connected to the line which can supply a low power supply potential (e.g., a GND line). The other of the pair of electrodes of the capacitor 708 can be supplied with a constant potential. For example, the other of the pair of electrodes of the capacitor 708 can be supplied with the low power supply potential (e.g., GND) or the high power supply potential (e.g., VDD). The other of the pair of electrodes of the capacitor 708 is electrically connected to the line which can supply a low power supply potential (e.g., a GND line).

The capacitor 707 and the capacitor 708 are not necessarily provided as long as the parasitic capacitance of the transistor, the wiring, or the like is actively utilized.

A control signal WE is input to the first gate (first gate electrode layer) of the transistor 709. As for each of the switch 703 and the switch 704, a conduction state or a non-conduction state between the first terminal and the second terminal is selected by the control signal RD which is different from the control signal WE. When the first terminal and the second terminal of one of the switches are in the conduction state, the first terminal and the second terminal of the other of the switches are in the non-conduction state.

A signal corresponding to data retained in the circuit 701 is input to the other of the source and the drain of the transistor 709. FIG. 14 illustrates an example in which a signal output from the circuit 701 is input to the other of the source and the drain of the transistor 709. The logic value of a signal output from the second terminal of the switch 703 (the other of the source and the drain of the transistor 713) is inverted by the logic element 706, and the inverted signal is input to the circuit 701 through the circuit 720.

In the example of FIG. 14, a signal output from the second terminal of the switch 703 (the other of the source and the drain of the transistor 713) is input to the circuit 701 through the logic element 706 and the circuit 720; however, this embodiment is not limited thereto. The signal output from the second terminal of the switch 703 (the other of the source and the drain of the transistor 713) may be input to the circuit 701 without its logic value being inverted. For example, in the case where a node in which a signal obtained by inversion of the logic value of a signal input from the input terminal is retained is provided in the circuit 701, the signal output from the second terminal of the switch 703 (the other of the source and the drain of the transistor 713) can be input to the node.

As the transistor 709 in FIG. 14, the transistor 100 described in Embodiment 1 can be used. As described in Embodiment 3, the transistor 709 preferably includes a second gate (second gate electrode layer). The control signal WE can be input to the first gate and the control signal WE2 can be input to the second gate. The control signal WE2 is a signal having a constant potential. As the constant potential, for example, a ground potential GND or a potential lower than a source potential of the transistor 709 is selected. The control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 709, and Icut of the transistor 709 can be further reduced. Note that as the transistor 709, the transistor without the second gate can be used.

Further, in FIG. 14, the transistors included in the memory element 700 except for the transistor 709 can each be a transistor in which a channel is formed in a layer formed using a semiconductor other than an oxide semiconductor or in the substrate 1190. For example, a transistor in which a channel is formed in a silicon layer or a silicon substrate can be used. Alternatively, a transistor in which a channel is formed in an oxide semiconductor layer can be used for all the transistors used for the memory element 700. Further alternatively, in the memory element 700, a transistor in which a channel is formed in an oxide semiconductor layer can be included besides the transistor 709, and a transistor in which a channel is formed in a layer or the substrate 1190 including a semiconductor other than an oxide semiconductor can be used for the rest of the transistors.

As the circuit 701 in FIG. 14, for example, a flip-flop circuit can be used. As the logic element 706, for example, an inverter, a clocked inverter, or the like can be used.

The semiconductor device of one embodiment of the present invention can, in a period during which the memory element 700 is not supplied with the power supply voltage, retain data stored in the circuit 701 by the capacitor 708 which is provided in the circuit 702.

The off-state current of a transistor in which a channel is formed in an oxide semiconductor layer is extremely low. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer is significantly lower than that of a transistor in which a channel is formed in silicon having crystallinity. Thus, when such a transistor including an oxide semiconductor is used for the transistor 709, a signal held in the capacitor 708 is retained for a long time also in a period during which the power supply voltage is not supplied to the memory element 700. The memory element 700 can accordingly retain the stored content (data) also in a period during which the supply of the power supply voltage is stopped.

Since the switch 703 and the switch 704 are provided, the memory element performs pre-charge operation; thus, the time required for the circuit 701 to retain original data again after the supply of the power supply voltage is restarted can be shortened.

In the circuit 702, a signal retained by the capacitor 708 is input to the gate of the transistor 710. Therefore, after supply of the power supply voltage to the memory element 700 is restarted, the signal retained by the capacitor 708 can be converted into the one corresponding to the state (the on state or the off state) of the transistor 710 to be read from the circuit 702. Consequently, an original signal can be accurately read even when a potential corresponding to the signal retained by the capacitor 708 fluctuates to some degree.

By applying the above-described memory element 700 to a storage device such as a register or a cache memory included in a processor, data in the storage device can be prevented from being lost owing to the stop of the supply of the power supply voltage. Further, shortly after the supply of the power supply voltage is restarted, the storage device can be returned to the same state as that before the power supply is stopped. Thus, the power supply can be stopped even for a short time in the processor or one or a plurality of logic circuits included in the processor. Accordingly, power consumption can be suppressed.

Although an example in which the storage element 700 is used in a CPU is described in this embodiment, the storage element 700 can also be used in a digital signal processor (DSP), a custom LSI, an LSI such as a programmable logic device (PLD), and a radio frequency identification (RF-ID).

This embodiment can be combined as appropriate with any of the other embodiments in this specification.

(Embodiment 6)

In this embodiment, examples of an electronic device which can include the transistor described in Embodiment 1, the storage device described in Embodiment 3 or 4, or the CPU and the like (including a DSP, a custom LSI, a PLD, and an RF-ID) described in Embodiment 5 is described.

The transistor described in Embodiment 1, the storage device described in Embodiment 3 or 4, and the CPU and the like described in Embodiment 5 can be applied to a variety of electronic devices (including game machines). Examples of the electronic devices include display devices of televisions, monitors, and the like, lighting devices, personal computers, word processors, image reproduction devices, portable audio players, radios, tape recorders, stereos, phones, cordless phones, mobile phones, car phones, transceivers, wireless devices, game machines, calculators, portable information terminals, electronic notebooks, e-book readers, electronic translators, audio input devices, video cameras, digital still cameras, electric shavers, IC chips, high-frequency heating appliances such as microwave ovens, electric rice cookers, electric washing machines, electric vacuum cleaners, air-conditioning systems such as air conditioners, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, freezers for preserving DNA, radiation counters, and medical equipment such as dialyzers and X-ray diagnostic equipment. In addition, the examples of the electronic devices include alarm devices such as smoke detectors, heat detectors, gas alarm devices, and security alarm devices. Further, the examples of the electronic devices also include industrial equipment such as guide lights, traffic lights, belt conveyors, elevators, escalators, industrial robots, and power storage systems. In addition, moving objects and the like driven by fuel engines and electric motors using power from non-aqueous secondary batteries are also included in the category of electronic devices. Examples of the moving objects include electric vehicles (EV), hybrid electric vehicles (HEV) which include both an internal-combustion engine and a motor, plug-in hybrid electric vehicles (PHEV), tracked vehicles in which caterpillar tracks are substituted for wheels of these vehicles, motorized bicycles including motor-assisted bicycles, motorcycles, electric wheelchairs, golf carts, boats or ships, submarines, helicopters, aircrafts, rockets, artificial satellites, space probes, planetary probes, and spacecrafts. Some specific examples of these electronic devices are illustrated in FIGS. 15A to 15C.

In a television set 8000 illustrated in FIG. 15A, a display portion 8002 is incorporated in a housing 8001. The display portion 8002 can display an image and a speaker portion 8003 can output sound. A storage device including the transistor of one embodiment of the present invention can be used for a driver circuit for operating the display portion 8002.

In addition, the television set 8000 may include a CPU 8004 for performing information communication or a memory. For the CPU 8004 and a memory, a CPU and a memory each of which includes the transistor of one embodiment of the present invention can be used.

An alarm device 8100 illustrated in FIG. 15A is a residential fire alarm, which is an example of an electronic device including a sensor portion 8102 for smoke or heat and a microcomputer 8101. Note that the microcomputer 8101 includes the transistor, the storage device, or the CPU described in any of the above embodiments.

An air conditioner which includes an indoor unit 8200 and an outdoor unit 8204 illustrated in FIG. 15A is an example of an electronic device including the transistor, the storage device, the CPU, or the like described in any of the above embodiments. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a CPU 8203, and the like. Although the CPU 8203 is provided in the indoor unit 8200 in FIG. 15A, the CPU 8203 may be provided in the outdoor unit 8204. Alternatively, the CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. By using any of the transistors described in the above embodiments for the CPU in the air conditioner, a reduction in power consumption of the air conditioner can be achieved.

An electronic refrigerator-freezer 8300 illustrated in FIG. 15A is an example of an electronic device including the transistor, the storage device, the CPU, or the like described in any of the above embodiments. Specifically, the electric refrigerator-freezer 8300 includes a housing 8301, a door for a refrigerator 8302, a door for a freezer 8303, a CPU 8304, and the like. In FIG. 15A, the CPU 8304 is provided in the housing 8301. When any of the transistors described in the above embodiments is used as the CPU 8304 of the electric refrigerator-freezer 8300, a reduction in power consumption of the electric refrigerator-freezer 8300 can be achieved.

FIGS. 15B and 15C illustrate an example of an electronic vehicle which is an example of an electronic device. An electric vehicle 9700 is equipped with a secondary battery 9701. The output of the electric power of the secondary battery 9701 is adjusted by a circuit 9702 and the electric power is supplied to a driving device 9703. The circuit 9702 is controlled by a processing unit 9704 including a ROM, a RAM, a CPU, or the like which is not illustrated. When any of the transistors described in the above embodiments is used as the CPU in the electric vehicle 9700, a reduction in power consumption of the electric vehicle 9700 can be achieved.

The driving device 9703 includes a DC motor or an AC motor either alone or in combination with an internal-combustion engine. The processing unit 9704 outputs a control signal to the circuit 9702 based on input data such as data of operation (e.g., acceleration, deceleration, or stop) by a driver or data during driving (e.g., data on an upgrade or a downgrade, or data on a load on a driving wheel) of the electric vehicle 9700. The circuit 9702 adjusts the electric energy supplied from the secondary battery 9701 in accordance with the control signal of the processing unit 9704 to control the output of the driving device 9703. In the case where the AC motor is mounted, although not illustrated, an inverter which converts a direct current into an alternate current is also incorporated.

This embodiment can be combined as appropriate with any of the other embodiments in this specification.

This application is based on Japanese Patent Application serial no. 2013-083799 filed with Japan Patent Office on Apr. 12, 2013 and Japanese Patent Application serial no. 2013-093160 filed with Japan Patent Office on Apr. 26, 2013, the entire contents of which are hereby incorporated by reference. 

What is claimed is:
 1. A semiconductor device comprising: a first oxide semiconductor layer over an insulating surface; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode and a drain electrode in direct contact with part of the first oxide semiconductor layer and part of the second oxide semiconductor layer; a third oxide semiconductor layer over the first oxide semiconductor layer and the second oxide semiconductor layer; a gate insulating film over the third oxide semiconductor layer; and a gate electrode over the gate insulating film, wherein a side edge of the first oxide semiconductor layer aligns with a side edge of one of the source electrode and the drain electrode, wherein the second oxide semiconductor layer wholly overlaps with the first oxide semiconductor layer, wherein the second oxide semiconductor layer is in direct contact with bottom surfaces of the source electrode and the drain electrode, wherein the third oxide semiconductor layer is in direct contact with top surfaces of the source electrode and the drain electrode, and wherein part of the source electrode and part of the drain electrode are provided between the second oxide semiconductor layer and the third oxide semiconductor layer.
 2. The semiconductor device according to claim 1, wherein a length (W_(T)) of a top surface of the second oxide semiconductor layer and a length (W_(S)) of one of side surfaces of the second oxide semiconductor layer in a cross section in a channel width direction satisfy a relation 0.3W_(S)≦W_(T)≦3W_(S).
 3. The semiconductor device according to claim 1, wherein a conduction band minimum of the first oxide semiconductor layer and a conduction band minimum of the third oxide semiconductor layer are closer to a vacuum level than a conduction band minimum of the second oxide semiconductor layer by 0.05 eV or more and 2 eV or less.
 4. The semiconductor device according to claim 1, wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprises an In—M—Zn oxide, wherein M is one selected from the group consisting of Al, Ti, Ga, Y, Zr, La, Ce, Nd, and Hf, and wherein an atomic ratio of M to In in each of the first oxide semiconductor layer and the third oxide semiconductor layer is higher than an atomic ratio of M to In in the second oxide semiconductor layer.
 5. The semiconductor device according to claim 1, wherein each of the source electrode and the drain electrode comprises a conductive material selected from the group consisting of Al, Cr, Cu, Ta, Ti, Mo, and W.
 6. The semiconductor device according to claim 1, wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprises a crystal.
 7. The semiconductor device according to claim 1, wherein c-axes of the second oxide semiconductor layer are aligned in a direction parallel to a normal vector of a surface of the second oxide semiconductor layer.
 8. The semiconductor device according to claim 1, wherein a crystal in a side surface portion of the second oxide semiconductor layer and a crystal in the third oxide semiconductor layer covering the side surface portion are connected by indium and oxygen.
 9. The semiconductor device according to claim 1, further comprising a capacitor over the insulating surface, wherein the capacitor comprises one of the source electrode and the drain electrode.
 10. An electronic device comprising the semiconductor device according to claim
 1. 11. A semiconductor device comprising: a first oxide semiconductor layer over an insulating surface; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode and a drain electrode in direct contact with part of the first oxide semiconductor layer and part of the second oxide semiconductor layer; a third oxide semiconductor layer over the first oxide semiconductor layer and the second oxide semiconductor layer; a gate insulating film over the third oxide semiconductor layer; and a gate electrode over the gate insulating film, wherein a side edge of the first oxide semiconductor layer aligns with a side edge of one of the source electrode and the drain electrode, wherein the second oxide semiconductor layer wholly overlaps with the first oxide semiconductor layer, wherein the second oxide semiconductor layer is in direct contact with bottom surfaces of the source electrode and the drain electrode, wherein the third oxide semiconductor layer is in direct contact with top surfaces of the source electrode and the drain electrode, wherein part of the source electrode and part of the drain electrode are provided between the second oxide semiconductor layer and the third oxide semiconductor layer, wherein a first region of the first oxide semiconductor layer is thinner than a second region of the first oxide semiconductor layer, and wherein the second region is in direct contact with the second oxide semiconductor layer.
 12. The semiconductor device according to claim 11, wherein a length (W_(T)) of a top surface of the second oxide semiconductor layer and a length (W_(S)) of one of side surfaces of the second oxide semiconductor layer in a cross section in a channel width direction satisfy a relation 0.3W_(S)≦W_(T)≦3W_(S).
 13. The semiconductor device according to claim 11, wherein a conduction band minimum of the first oxide semiconductor layer and a conduction band minimum of the third oxide semiconductor layer are closer to a vacuum level than a conduction band minimum of the second oxide semiconductor layer by 0.05 eV or more and 2 eV or less.
 14. The semiconductor device according to claim 11, wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprises an In—M—Zn oxide, wherein M is one selected from the group consisting of Al, Ti, Ga, Y, Zr, La, Ce, Nd, and Hf, and wherein an atomic ratio of M to In in each of the first oxide semiconductor layer and the third oxide semiconductor layer is higher than an atomic ratio of M to In in the second oxide semiconductor layer.
 15. The semiconductor device according to claim 11, wherein each of the source electrode and the drain electrode comprises a conductive material selected from the group consisting of Al, Cr, Cu, Ta, Ti, Mo, and W.
 16. The semiconductor device according to claim 11, wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprises a crystal.
 17. The semiconductor device according to claim 11, wherein c-axes of the second oxide semiconductor layer are aligned in a direction parallel to a normal vector of a surface of the second oxide semiconductor layer.
 18. The semiconductor device according to claim 11, wherein a crystal in a side surface portion of the second oxide semiconductor layer and a crystal in the third oxide semiconductor layer covering the side surface portion are connected by indium and oxygen.
 19. The semiconductor device according to claim 11, further comprising a capacitor over the insulating surface, wherein the capacitor comprises one of the source electrode and the drain electrode.
 20. An electronic device comprising the semiconductor device according to claim
 11. 